Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.6. Commands and Responses

The host controller communicates with the SDM using command and response packets via the Mailbox Client Intel® FPGA IP.

The first word of the command and response packets is a header that provides basic information about the command or response.

Figure 3. Command and Response Header Format
Note: The LENGTH field in the command header must match the command length of corresponding command.

The following table describes the fields of the header command.

Table 12.  Command and Response Header Description
Header Bit Description
Reserved [31:28] Reserved.
ID [27:24] The command ID. The response header returns the ID specified in the command header. Refer to Operation Commands for command descriptions.
0 [23] Reserved.
LENGTH [22:12] Number of words of arguments following the header. The Mailbox Client Intel® FPGA IP responds with an error if a wrong number of words of arguments is entered for a given command.

If there is a mismatch between the command length specified in the command header and the number of words sent, the Mailbox Client Intel® FPGA IP raises bit 3 of the Interrupt Status Register (COMMAND_INVALID) and the Mailbox Client Intel® FPGA IP must be reset.

Reserved [11] Reserved. Must be set to 0.
Command Code/Error Code [10:0] Command Code specifies the command. The Error Code indicates whether the command succeeded or failed.

In the command header, these bits represent command code. In the response header, these bits represent error code. If the command succeeds, the Error Code is 0. If the command fails, refer to the error codes defined in the Error Code Responses.


Section Content
Operation Commands
Error Code Responses
Error Code Recovery

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