Witig Commad Packet

Wite Commad Desciptio

Whe you sed a commad to the SDM, wite the commad wod ito commad egiste, which is the base addess. To stay i syc with the hadwae, while the commad legth (t) is geate tha zeo, wite the heade ad agumets i the Commad egiste which is (base addess + 0). Cotiue witig the heade o agumets, oe wod at the time, i the Commad egiste (base addess + 0) while thee is available fee space i the FIFO fo commads ( > t). Wite the last wod to the Commad last wod egiste which is (base addess +1). Fo commads with o agumets, wite the heade to the Commad last wod egiste, (base addess +1).

Readig fom (base addess + 2) shows the emaiig available fee space i the FIFO fo commads. The commad FIFO ca become full whe the SDM is busy. The Mailbox Cliet Itel® FPGA IP equies 3 clock cycles to update the Commad FIFO empty space value. You ca begi eadig the Commad FIFO empty space value 3 clock cycles afte witig the commad to the IP.

You must check the Commad FIFO empty space egiste, (base addess + 2) befoe poceedig to wite ito the Commad o Commad last wod egistes. The behavio of the Mailbox Cliet Itel® FPGA IP is udefied if you wite to (base addess + 0) ad (base addess + 1) while the FIFO is full. The wite data is discaded.

I the above sceaio, the Mailbox Cliet Itel® FPGA IP expects a 3-wod espose (commad heade ad 2 data wods). Howeve, the SDM oly etus a oe-wod espose, which is the eo espose code.

You must sed commads i the coect ode to the Commad o Commad last wod egiste, as descibed i Witig Commad Packet. Failue to sed commads i the coect ode ca esult i loss of sevices fo all mailbox cliets, icludig the followig stadaloe IP coes:

• Tempeatue Seso Itel® FPGA IP
• Voltage Seso Itel® FPGA IP
• Chip ID Itel® FPGA IP
• Advaced SEU Detectio Itel® FPGA IP
• Patial Recofiguatio Cotolle Itel® FPGA IP
• Patial Recofiguatio Exteal Cofiguatio Cotolle Itel® FPGA IP

Readig Respose Packet

Read Commad Desciptio

1. Read (base addess + 8) to check if bit 0 of Iteupt status egiste is 1, to idicate the valid data is available fo the maste to ead. You ca poll the Iteupt status egiste cotiuously util bit 0 is 1.
2. Read (base addess + 6) to check the SOP (stat of packet), EOP (ed of packet), ad the Respose FIFO fill level ().

   To ead multiple wods, complete the followig steps:

   1. If SOP = 1 ad EOP = 0, the espose has multiple wods.
   2. If the Respose FIFO fill level () is o-zeo, the FIFO has valid data.
   3. Fo example, if you pefom a QSPI_READ opeatio to ead 10 wods fom quad SPI flash, a etu value of 0x0000002d idicates that the SDM wote 11 wods to the espose FIFO. The 11 wods compise a espose heade wod ad 10 data wods.
   To ead a sigle wod, complete the followig steps:

   1. If SOP = 1 ad EOP = 1, the espose has a sigle wod.
   2. If the Respose FIFO fill level is o-zeo, the FIFO has valid data.
   3. A etu value of 0x00000007 idicates that the SDM wote a sigle wod to the espose FIFO. This sigle is both the stat ad ed of the sigle-cycle packet.
3. Read the espose heade at (base addess + 5). The LENGTH value specifies the umbe of wods i the espose. Poceed to step 4 if the espose eo code is zeo. The espose eo code is o-zeo fo usuccessful commads. Refe to Eo Codes fo moe ifomatio.
4. Whe the legth of the espose heade (t) is geate tha zeo (LENGTH > 1) , ead (base addess + 5) to etieve the espose data. While cotiuously eadig the espose data, you must also cotiuously poll (base addess + 6) to check the Respose FIFO fill level (). Fo the fial wod of the packet, the Respose FIFO fill level () ad EOP value ae expected to be 1 at the same time. You must check fo EOP = 1 befoe poceedig to ead the fial wod fom the espose data.
   Note:

   If the espose FIFO is empty, the etu data is udefied. You must check the Iteupt status egiste to esue that valid data is available. You must veify that the Respose FIFO fill level () is o-zeo befoe eadig the espose data.

   Esue that you ead o flush out the cotet i the espose FIFO befoe issuig a ew commad to the mailbox. Cotiuously sedig commads without eadig back the valid data fom the espose FIFO gadually fills the espose FIFO. Whe the espose FIFO oveflows the SDM feezes.

   If the SDM feezes you must ecofigue the device. The Quatus® Pime softwae suppots device ecofiguatio statig i vesio 19.1. Fo ealie vesios of the Quatus® Pime softwae, powe cycle the device to ecove.

Restictios

1. You ca oly issue oe equest ad ead back the espose befoe issuig a ew equest to the Mailbox Cliet Itel® FPGA IP.
2. Fo Agilex™ 5 devices, oly oe istatiatio of the Agilex™ 5 Mailbox Cliet Itel® FPGA IP is suppoted
3. Fo Statix® 10 devices, multiple mailbox cliets i the fom of stadaloe IP coes may have bee used i a desig to sed diffeet commads. I this case, do ot istatiate moe tha six mailbox cliets i you desig. Fo desigs equiig moe tha six mailbox cliets, use the Mailbox Cliet Itel® FPGA IP to eplace the followig stadaloe IP coes:
   • Tempeatue Seso Itel® FPGA IP
   • Voltage Seso Itel® FPGA IP
   • Chip ID Itel® FPGA IP
   • Seial Flash Mailbox Cliet Itel® FPGA IP
   Note: Agilex™ devices do ot suppot these stadaloe IP coes. Istead, use the Mailbox Cliet Itel® FPGA IP o Agilex™ 5 Mailbox Cliet Itel® FPGA IP.