Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide

Documet Vesio Quatus® Pime Vesio Chages
2024.11.04 24.3
  • Updated the Commad List ad Desciptio table i the Opeatio Commads sectio with the followig chages.
    • Impoved the example fo INSERT_SAFE_SEU_ERROR.
    • Updated Wod 2 ad Wod 5 fo CONFIG_STATUS.
    • Updated desciptio fo QSPI_ERASE. .
    • Updated desciptio fo GET_CONFIGURATION_TIME
  • Chaged the commad heade field fom Cliet to Reseved i the Commads ad Resposes sectio.
  • Added fileames specific to Agilex™ 5 suppot i the followig sectios:
    • Mailbox Cliet HAL API
    • Mailbox Cliet Dive API
    • LibRSU HAL API
2024.07.08 24.2
  • Updated the Commad List ad Desciptio table i the Opeatio Commads sectio with the followig chages.
    • Added GET_I2C_TELEMETRY.
    • Updated desciptio fo CONFIG_STATUS.
2024.04.01 24.1
  • Added Agilex 5 Mailbox Cliet Itel® FPGA IP.
  • Added suppot fo Agilex™ 5 devices.
  • Added the Release Ifomatio sectio.
  • Added lik to a KDB i the Mailbox Cliet Dive API sectio.
  • Added the followig commads to the Commad List ad Desciptio table i the Opeatio Commads sectio.
    • READ_SEU_STATS
    • INSERT_SAFE_SEU_ERROR
    • INSERT_ECC_ERROR
Documet Vesio Quatus® Pime Vesio IP Vesio Chages
2023.12.04 23.4 21.0.0 Added additioal Mio Eo Code i CONFIG_STATUS ad RSU_STATUS Mio Eo Code Desciptios table i Appedix: CONFIG_STATUS ad RSU_STATUS Eo Code Desciptios sectio.
2023.10.02 23.3 21.0.0 Added the followig to the Commad List ad Desciptio table i the Opeatio Commads sectio.
  • READ_SEU_ERROR
  • STATUS_VR
2023.08.01 23.2 21.0.0
  • Updated the desciptio fo the QSPI_OPEN ad QSPI_SET_CS commads i the Commad List ad Desciptio table i sectio Opeatio Commads.
  • Updated the eo code ecovey fo value C i the Eo Code Recovey fo Kow Eo Codes table i the Eo Code Recovey sectio.
  • Added ow fo QSPI_READ_SHA512 commad i the Commad List ad Desciptiotable i sectio Opeatio Commads.
  • Updated the Mailbox Cliet Itel® FPGA IP Itefaces figue i the Mailbox Cliet Itel® FPGA IP Coe Iteface Sigals sectio to iclude avmm_waitequest.
  • Updated the Avalo® Memoy-Mapped Iteface table i the Avalo® Memoy-Mapped Iteface sectio to iclude avmm_waitequest.
  • Updated the mailbox_cliet_flash _ease_blocktable i the Mailbox Cliet Dive API sectio to eplace Kbytes with KB.
Documet Vesio Quatus® Pime Vesio Chages
2023.04.10 22.4
  • Added lik to a KDB i the Mailbox Cliet with Avalo® Steamig Iteface Itel FPGA IP Oveview sectio.
  • Updated cotet i the LibRSU HAL API sectio to bette claify how to obtai ZLIB.
  • Updated poduct family ame to " Itel Agilex® 7".
  • Reamed Avalo ST ad Avalo MM to Avalo steamig iteface ad Avalo memoy-mapped iteface.
2022.12.19 22.4
  • Added GET_CONFIGURATION_TIME ad QSPI_READ_SHA commad i the Commad List ad Desciptio table.
  • Updated default value ad desciptio fo su_potected_slot i the Cofiguatio Paamete table.
2022.09.26 22.3
  • Updated the GET_VOLTAGE commad ow i the Commad List ad Desciptio table.
  • Revised Usig the Mailbox Cliet Itel FPGA IP. Removed the "Wait 10 ms betwee back to back commads to the SDM mailbox" i Restictios.
  • Added a ote to Table: Device Family Suppot.
  • Revised the desciptio fo LENGTH heade i Table: Commad ad Respose Heade Desciptio.
  • Revised ote about eabled bits i Iteupt Eable Registe.
  • Added efeece to Itel® Agilex™ Device Secuity Use Guide i Eablig Cyptogaphic Sevices.
  • Revised QSPI_SET_CS commad desciptio i the Commad List ad Desciptio table.
  • Edited the title fo Nios II HAL Dive to Nios II ad Nios V Pocessos Hal Dive
    • Added text to specify the use of Quatus® Pime Po Editio softwae vesio pio 21.4.
  • Added the followig topics:
    • Mailbox Cliet HAL API
    • LibRSU HAL API
    • Cofiguatio Paamete
    • Eo Codes
    • Usig LibRSU HAL API without Valid SPT o CPB
    • Data Type
    • Fuctios
    • RSU Cliet API
2022.04.04 22.1
  • Updated istaces of AXI taget to AXI maage.
  • Updated cypto sevice-specific paamete ame fom HAS_OFFLOAD to Eable Cypto Sevice.
  • Added bit 8 ad bit 9 i the followig tables:
    • Iteupt Eable Registe
    • Iteupt Status Registe
  • Updated the Commad List ad Desciptio table.
    • Updated pi status desciptio fo the CONFIG_STATUS commad.
    • Removed the REBOOT_HPS commad.
2021.11.10 21.3 Made the followig chages:
  • Updated the device family suppot fo Itel® Agilex™ devices.
  • Added ew sectio descibig suppot fo cyptogaphic sevices.
  • Revised Iteupt Eable Registe table. Added ew egistes:
    • EN_CRYPTO_MEMORY_TIMEOUT
    • EN_CRYPTO_ERROR_RECOVERY_PROGRESS
  • Revised Iteupt Status Registe table. Added ew iteupts:
    • CRYPTO_MEMORY_TIMEOUT
    • CRYPTO_ERROR_RECOVERY_PROGRESS
  • Revised Commad List ad Desciptio table. Updated desciptio fo:
    • CONFIG_STATUS
    • RSU_STATUS
  • Updated the mailbox_cliet_sed_cmd commad i the Dive API sectio.
    • Revised espose buffe legth declaatio fom a poite (alt_u32* esp_buf_le) to a itege (alt_u32 esp_buf_le).
    • Added a ENOBUFS-elated footote.
2021.06.21 21.2 Made the followig chages:
  • Revised Iteupt Eable Registe. Added ote about eable bits.
  • Revised Commad List ad Desciptio table. Updated desciptio fo:
    • RSU_STATUS
    • QSPI_OPEN
    • QSPI_SET_CS
    • QSPI_ERASE
  • Revised Read Commad Desciptio i the Usig the Mailbox Cliet Itel® FPGA IP . Added attetio ote about accessig SDM ove a Avalo® memoy-mapped iteface.
  • Revised Nios® II HAL Dive. Added text about absolute addessig to the quad SPI.
  • Added mailbox_cliet_flash_get_ifo opeatio i the Dive API sectio.
  • Removed Dive API Applicatio topic. The cotet was moved to a file efeeced i the Dive API sectio.
  • Updated Appedix: CONFIG_STATUS ad RSU_STATUS Eo Code Desciptios. Added 0xD00D - 0xD013 mio eo codes desciptios.
2021.03.29 21.1 Made the followig chages:
  • Revised the Flow Chat fo Respose Packet figue ad the Read Commad Desciptio sectio.
  • Revised RSU_IMAGE_UPDATE desciptio i the Commad List ad Desciptio table.
  • Added ew topics:
    • Nios® II HAL Dive
    • Dive API
    • Dive API Applicatio
  • Restuctued Opeatio Commads. Moved majo ad mio eo code desciptios fo the CONFIG_STATUS ad RSU_STATUS commads to the Appedix: CONFIG_STATUS ad RSU_STATUS Eo Code Desciptios.
2020.12.14 20.4 Made the followig chages:
  • Revised block diagam desciptio i the Mailbox Cliet Itel® FPGA IP Use Guide topic.
  • Updated the Mailbox Cliet Itel® FPGA IP System Block Diagam figue. The figue depicts vaious ways to commuicate with Mailbox Cliet IP.
  • Added impotat ote about esettig QSPI flash i the Opeatio Commads topic.
  • Updated the Commad List ad Desciptio table:
    • Revised GET_TEMPERATURE commad desciptio. Claified diffeece betwee Statix® 10 ad devices.
    • Revised RSU_IMAGE_UPDATE commad desciptio.
      • Added text about esettig QSPI flash.
      • Added text descibig behavio betwee the exteal host ad FPGA.
      • Removed text: Retus a o-zeo espose if the device is aleady pocessig a cofiguatio commad.
    • Updated QSPI_WRITE ad QSPI_READ desciptios to specify that the maximum tasfe size is 4 kilobytes o 1024 wods.
    • Coected espose legth fom 1 to 0 fo the QSPI_OPEN, QSPI_CLOSE ad QSPI_SET_CS commad.
    • Revised QSPI_OPEN, QSPI_WRITE, QSPI_READ_DEVICE_REG, ad QSPI_WRITE_DEVICE_REG desciptios.
    • Added a ew commad: REBOOT_HPS.
  • Added ew topic: Eo Code Recovey.
  • Revised Time Registes topic. Added foototes ad updated egistes desciptio.
  • Updated Flow Chat fo Readig Respose Packet figue.
2020.10.05 20.3 Made the followig chages:
  • Revised GET TEMPERATURE commad desciptio fo Itel® Agilex™ devices i the Commad List ad Desciptio table.
  • Added ecommedatio about the eset sychoize i the Mailbox Cliet FPGA Coe Sigals sectio.
  • Updated the Eo Codes table. Added ew eo code esposes:
    • HW_ERROR
    • COMMAND_SPECIFIC_ERROR
2020.06.30 20.2 Made the followig chages:
  • Revised LENGTH ad Commad Code/Eo Code desciptios i the Commad ad Respose Heade Desciptio table.
  • Revised GET_TEMPERATURE commad desciptio i the Commad List ad Desciptio table.
  • Removed UNKNOWN_BR commad fom the Eo Codes table.
  • Added ew time featue to hadle the eo detectio fo the icomplete tasactio timeout eo ad the SDM backpessue timeout fatal eo.
  • Added suppot fo a EOP_TIMEOUT iteupt which idicates that the full commad did ot iclude the EOP.
  • Added suppot fo a BACKPRESSURE_TIMEOUT iteupt which idicates that a eo withi the SDM occued.
  • Removed SD/MMC text fom the CLIENT_ID_NO_MATCH desciptio i the Eo Codes table.
  • Updated wite ad ead commad desciptios i the Usig the Mailbox Cliet Itel FPGA IP sectio.
2020.04.13 20.1 Made the followig chages:
  • Added the followig estictio to the defiitio of QSPI_SET_CS: Access to the QSPI flash memoy devices usig SDM_IO pis is oly available fo the AS x4 cofiguatio scheme, JTAG cofiguatio, ad a desig compiled fo ASx4 cofiguatio. Fo the Avalo® ST cofiguatio scheme, you must coect QSPI flash memoies to GPIO pis.
  • Added the followig text to the defiitio of the Failig image field of the RSU_STATUS commad:
    Note: A isig edge o CONFIG to ecofigue fom ASx4, does ot clea this field. Ifomatio about failig image oly updates whe the Mailbox Cliet eceives a ew RSU_IMAGE_UPDATE commad ad successfully cofigues fom the update image.
  • Added RSU_NOTIFY commad i the Commad List ad Desciptio table.
  • Revised the Flow Chat fo Witig Commad Packet ad Flow Chat fo Readig Respose Packet to iclude the coect sequece fo witig commads ito a commad FIFO ad eadig espose packets fom a espose FIFO. Updated coespodig Wite Commad Desciptio ad Read Commad Desciptio sectios.
2020.03.17 19.3 Made the followig chages:
  • Updated the Eo Codes table:
    • Reamed INVALID_COMMAND_PARAMETERS to INVALID_LENGTH.
    • Chaged COMMAND_INVALID_ON_SOURCE hex value fom 5 to 6.
    • Chaged CLIENT_ID_NO_MATCH hex value fom 6 to 8.
    • Chaged INVALID_ADDRESS hex value fom 7 to 9.
    • Added AUTHENTICATION_FAIL commad.
    • Chaged TIMEOUT hex value fom 8 to B.
    • Chaged HW_NOT_READY hex value fom 9 to C.
2019.09.30 19.3 Made the followig chages:
  • Added device suppot fo the Itel® Agilex™ device.
  • Added suppot fo a COMMAND_INVALID iteupt which idicates the commad legth specified i the heade does ot match the actual commad set.
  • Chaged ame of the IP fom Mailbox Cliet Statix® 10 FPGA IP to Mailbox Cliet Itel FPGA IP.
  • Revised itoductio icludig the Figue 1: Mailbox Cliet Itel FPGA IP System Block Diagam.
  • Revised the Flow Chat fo Witig Commad Packet ad Flow Chat fo Readig Respose Packet to iclude logic to hadle multiple wod commads ad esposes.
  • Chaged efeeces to ames of all mailbox cliet IPs. The mailbox cliets IP o loge iclude the Statix® 10 FPGA i thei ames.
  • Added efeece to AN 891: Usig the Reset Release Itel FPGA IP.
  • Added efeece to the Itel® Agilex™ Powe Maagemet Use Guide.
  • Updated the desciptio of the GET_TEMPERATURE commad to say the mask agumet is optioal. Whe omitted, the commad etus the tempeatue fo seso 0.
  • Updated the RSU_STATUS commad to say the highest pioity failig image, ot the last failig image. The eo ifomatio is fo the fist failig image which is the highest pioity failig image.
  • Added desciptios fo CONFIG_STATUS ad RSU_STATUS majo ad mio eo codes.
  • Added HPS_COLDRESET ad HPS_WARMRESET to the list of soft fuctios fo the CONFIG_STATUS commad.
  • Added Mailbox Cliet Itel FPGA IP Use Guide Achives topic.
  • Added the followig Itel FPGA IPs to the list of IPs that equie pope use of the Commad ad Commad last egistes:
    • Advaced SEU Detectio Itel IP
    • Patial Recofiguatio Cotolle Itel IP
    • Patial Recofiguatio Exteal Cofiguatio Cotolle Itel FPGA IP
    • Edited etie use guide fo claity ad style.
Documet Vesio Chages
2019.04.19
  • Updated the Featue Desciptio topic.
  • Added a ote to Figue: Commad ad Respose Heade Fomat.
  • Updated Table: Mailbox Cliet Itel® Statix® 10 FPGA IP Commad ad Respose Heade Desciptio to update the desciptio fo bit[11] of the commad ad espose heade.
  • Updated Table: Commad List ad Desciptio to update the desciptios fo CONFIG_STATUS ad RSU_STATUS.
  • Reamed topic title Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Avalo® -MM Iteface to Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Sigals.
  • Reamed table title Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Avalo® -MM Iteface to Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Sigal Desciptio.
  • Updated Table: Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Sigal Desciptio to iclude ifomatio o clock ad eset sigals.
  • Updated Table: Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Avalo® -Memoy Map to emove uget commad ad uget FIFO empty space.
  • Updated the Usig the Mailbox Cliet Itel® Statix® 10 FPGA IP Coe topic:
    • Added ew Figues: Flow Chat fo Witig Commad Packet ad Flow Chat fo Readig Respose Packet.
    • Added a ew sectio—Restictios.
    • Updated the desciptio i the Witig Commad Packet sectio.
  • Updated the Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Use Case Examples topic.
  • Made editoial updates thoughout the documet.
2019.03.14
  • Updated the Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Use Guide topic.
  • Updated Figue: Mailbox Cliet Itel® Statix® 10 FPGA IP Coe ad System Block Diagam.
  • Updated Table: Commad List ad Desciptio:
    • Updated the colum ame Numbe of Commads to Commad Legth.
    • Updated the colum ame Numbe of Resposes to Respod Legth.
    • Coected the desciptio fo QSPI_READ, QSPI_WRITE, ad QSPI_ERASE.
2019.02.25
  • Updated the desciptio i the Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Use Guide topic.
  • Updated Figue: Mailbox Cliet Itel® Statix® 10 FPGA IP Coe Use Guide.
  • Updated Table: Iteupt Status Registe to update the desciptio fo DATA_VALID.
  • Reamed the followig topic titles:
    • Commads ad Eo Codes to Commads ad Resposes
    • Commads to Opeatio Commads.
  • Updated Table: Mailbox Cliet Statix® 10 FPGA IP Commad ad Respose Heade Desciptio to update the desciptios fo Legth ad Commad Code/Eo Code.
  • Updated Table: Commad List ad Desciptio:
    • Updated the umbe of esposes ad desciptio fo CONFIG_STATUS.
    • Updated the umbe of esposes fo RSU_STATUS.
    • Updated the desciptios fo QSPI_READ, QSPI_WRITE, ad QSPI_ERASE.
  • Updated Table: Mailbox Cliet Statix® 10 FPGA IP Eo Code Resposes ad Desciptio to update the desciptio fo UNKNOWN_BR.
  • Updated the Witig Commad Packet ad Readig Commad Packet sectios i the Usig the Mailbox Cliet Itel® Statix® 10 FPGA IP Coe topic.
  • Updated the Mailbox Cliet Itel Statix 10 FPGA IP Coe Use Case Examples topic.
  • Removed the followig topics:
    • Example 1: Readig eASIC™ N5X IDCODE ad Voltage
    • Example 2: Read ad Wite EPCQ-L o QSPI Devices
2018.10.15
  • Updated Table: Commad List ad Desciptio to iclude the followig commads:
    • Updated the desciptios fo GET_TEMPERATURE.
    • Added ew commads:
      • RSU_IMAGE_UPDATE
      • CONFIG_STATUS
      • RSU_STATUS
    • Removed the commad GET_DESIGNHASH.
  • Updated Table: Eo Code Resposes ad Desciptio to update the value of the followig eo code esposes:
    • NOT_CONFIGURED
    • ALT_SDM_MBOX_RESP_DEVICE_BUSY
    • ALT_SDM_MBOX_RESP_NO_VALID_RESP_AVAILABLE
    • ALT_SDM_MBOX_RESP_ERROR
  • Added a ote to Figue: Mailbox Cliet Itel Statix 10 FPGA IP Coe Block Diagam.
  • Made mio editoial updates.
2018.02.14 Iitial elease.
Level Two Title