Visible to Intel only — GUID: pmg1494231858531
Ixiasoft
1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
Visible to Intel only — GUID: pmg1494231858531
Ixiasoft
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
The host commuicates with the Mailbox Cliet Itel® FPGA IP ove its Avalo® memoy-mapped iteface.
Though the AXI maage iteface, the cypto sevice has access to the lowest 1GB of memoy, with a maximum data size of 512 MB pe each ead ad wite opeatio.
Note: Fo Agilex™ 7 ad Agilex™ 5 devices, the AXI maage iteface is available if you eabled the Eable Cypto Sevice paamete.
The followig figue illustates the Mailbox Cliet Itel® FPGA IP itefaces.
Figue 2. Mailbox Cliet Itel® FPGA IP ItefacesThe AXI maage iteface is oly available i the Agilex™ 7 ad Agilex™ 5 devices with the Eable Cypto Sevice paamete eabled.
Note: Fo ifomatio about the AXI maage iteface, efe to the AXI Maage Iteface table.
Note: The avmm_waitequest sigal is madatoy i Quatus® Pime softwae vesio 23.2 o late.