Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.1. Release Information

Itel® FPGA IP vesios match the Quatus® Pime Desig Suite softwae vesios util v19.1. Statig i Quatus® Pime Desig Suite softwae vesio 19.2, Itel® FPGA IP has a ew vesioig scheme.

The Itel® FPGA IP vesio (X.Y.Z) umbe ca chage with each Quatus® Pime softwae vesio. A chage i:

  • X idicates a majo evisio of the IP. If you update the Quatus® Pime softwae, you must egeeate the IP.
  • Y idicates the IP icludes ew featues. Regeeate you IP to iclude these ew featues.
  • Z idicates the IP icludes mio chages. Regeeate you IP to iclude these chages.
The IPs listed i this sectio ae efeed to collectively as Mailbox Cliet Itel® FPGA IP thoughout this documet uless othewise oted.
Table 1.   Mailbox Cliet Itel® FPGA IP Release Ifomatio
Item Desciptio
IP Vesio 22.0.0
Quatus® Pime Po Editio Vesio 24.2
Release Date 2024.07.08
Table 2.  Agilex 5 Mailbox Cliet Itel® FPGA IP Release IfomatioThis IP is used exclusively with Agilex™ 5 devices.
Item Desciptio
IP Vesio 1.0.0
Quatus® Pime Po Editio Vesio 24.2
Release Date 2024.07.08
Related Ifomatio
Level Two Title