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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.11.2.2. Error Codes
I case of success, the LibRSU HAL APIs etu the value 0; othewise, the LibRSU HAL APIs etu the egative values show below.
#defie ELIB 1 /* Eo Libay */ #defie ECFG 2 /* Eo Cofiguatio */ #defie ESLOTNUM 3 /* Eo Slot Numbe */ #defie EFORMAT 4 /* Eo Fomat */ #defie EERASE 5 /* Eo Ease */ #defie EPROGRAM 6 /* Eo Pogam */ #defie ECMP 7 /* Eo Compae */ #defie ESIZE 8 /* Eo Size */ #defie ENAME 9 /* Eo Name */ #defie EFILEIO 10 /* Eo File IO */ #defie ECALLBACK 11 /* Eo Callback */ #defie ELOWLEVEL 12 /* Eo Low Level */ #defie EWRPROT 13 /* Eo Wite Potectio */ #defie EARGS 14 /* Eo Agumet */ #defie ECORRUPTED_CPB 15 /* Eo Coupted CPB */ #defie ECORRUPTED_SPT 16 /* Eo Coupted SPT */