Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.2. Avalon® Memory-Mapped Interface

The Avalo® memoy-mapped iteface is stadad memoy-mapped iteface. Fo detailed defiitios of these sigals, efe to the Avalo® Memoy-Mapped Iteface chapte i the Avalo® Iteface Specificatios.

Table 5.   Avalo® Memoy-Mapped Iteface
Sigal Role Width Diectio Desciptio
avmm_addess 4 Iput Avalo® memoy-mapped iteface addess.
avmm_wite 1 Iput Avalo® memoy-mapped iteface wite equest.
avmm_ead 1 Iput Avalo® memoy-mapped iteface ead equest.
avmm_witedata 32 Iput Avalo® memoy-mapped iteface wite data bus.
avmm_eaddata 32 Output Avalo® memoy-mapped iteface ead data bus.
avmm_eaddatavalid 1 Output Avalo® memoy-mapped iteface ead data valid.
avmm_waitequest 1 Output Avalo® memoy-mapped iteface wait equest.
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