Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.11.1. Mailbox Client HAL API

The Mailbox Client HAL API is available for this controller in the following software files.
  • For Stratix® 10 and Agilex™ 7 devices:
    • altera_s10_mailbox_client.h
    • altera_s10_mailbox_client.c
    • altera_s10_mailbox_client_flash.h
    • altera_s10_mailbox_client_flash.c
  • For Agilex™ 5 devices:
    • intel_mailbox_client.h
    • intel_mailbox_client.c
    • intel_mailbox_client_flash.h
    • intel_mailbox_client_flash.c
These files implement the mailbox client core device driver for the HAL system library. The HAL driver provides exclusive functions on QSPI flash device-related operations to simplify your design flow.

To use the HAL API, enable altera_safeclib in the BSP Software Package from BSP Editor for Quartus® Prime Pro Edition software version prior to 21.4. Enter mailbox_client_open() function to start the HAL API. Note that the interrupt connection to the processor is necessary to use the HAL API.

The absolute addressing to the quad SPI memory specifies all the offset-related variables. You must complete the quad SPI operation by calling mailbox_client_flash_open() before any flash operation, and mailbox_client_flash_close() at the end of any flash operation.


Section Content
Mailbox Client Driver API

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