Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.6. Commands and Responses

The host cotolle commuicates with the SDM usig commad ad espose packets via the Mailbox Cliet Itel® FPGA IP.

The fist wod of the commad ad espose packets is a heade that povides basic ifomatio about the commad o espose.

Figue 3. Commad ad Respose Heade Fomat
Note: The LENGTH field i the commad heade must match the commad legth of coespodig commad.

The followig table descibes the fields of the heade commad.

Table 12.  Commad ad Respose Heade Desciptio
Heade Bit Desciptio
Reseved [31:28] Reseved.
ID [27:24] The commad ID. The espose heade etus the ID specified i the commad heade. Refe to Opeatio Commads fo commad desciptios.
0 [23] Reseved.
LENGTH [22:12] Numbe of wods of agumets followig the heade. The Mailbox Cliet Itel® FPGA IP espods with a eo if a wog umbe of wods of agumets is eteed fo a give commad.

If thee is a mismatch betwee the commad legth specified i the commad heade ad the umbe of wods set, the Mailbox Cliet Itel® FPGA IP aises bit 3 of the Iteupt Status Registe (COMMAND_INVALID) ad the Mailbox Cliet Itel® FPGA IP must be eset.

Reseved [11] Reseved. Must be set to 0.
Commad Code/Eo Code [10:0] Commad Code specifies the commad. The Eo Code idicates whethe the commad succeeded o failed.

I the commad heade, these bits epeset commad code. I the espose heade, these bits epeset eo code. If the commad succeeds, the Eo Code is 0. If the commad fails, efe to the eo codes defied i the Eo Code Resposes.


Sectio Cotet
Opeatio Commads
Eo Code Resposes
Eo Code Recovey

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