Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.3. AXI Manager Interface

The AXI maage iteface is a stadad advaced extesible iteface (AXI). This iteface is accessible whe you eabled the cypto sevices featues. The cypto sevices featues ae available fo the Agilex™ 7 ad Agilex™ 5 devices.
Table 6.  AXI Maage ItefaceThe table displays commad, espose, ad uget iteface sigals.
Sigal Role Width Diectio Desciptio
AXI Maage Clock ad Reset Sigals
axi_i_clk 1 Iput

AXI* iteface clock.

axi_i_eset 1 Iput

AXI* iteface eset.

AXI Maage Wite Addess Chael Sigals
axi_taget_awid 4 Output AXI* idetificatio tag fo wite tasactio.
axi_taget_awadd 32 Output AXI* addess of the fist tasfe i a wite tasactio.
axi_taget_awle 8 Output AXI* legth. Idetifies the exact umbe of data tasfes i a wite tasactio.
axi_taget_awsize 3 Output

AXI* size. Idetifies the umbe of bytes i each data tasfe i a wite tasactio.

axi_taget_awbust 2 Output

AXI* bust type. Idicates how addess chages betwee each tasfe i a wite tasactio.

axi_taget_awlock 1 Output

Povides ifomatio about the atomic chaacteistics of a AXI* wite tasactio.

axi_taget_awcache 4 Output Idicates how a wite tasactio is equied to pogess though a system.
axi_taget_awpot 3 Output

Potectio attibutes of a wite tasactio: pivilege, secuity level, ad access type.

axi_taget_awqos 4 Output

Quality of Sevice idetifie fo a wite tasactio

axi_taget_awvalid 1 Output

AXI* valid sigal fo a wite tasactio.

Idicates that the wite addess chael sigals ae valid.

axi_taget_awuse 5 Output Use-defied extesio fo the wite addess chael.
axi_taget_aweady 1 Iput

AXI* eady sigal fo wite addess.

Idicates that a tasfe o the wite addess chael ca be accepted.

AXI Maage Wite Data Chael Sigals
axi_taget_wdata 64 Output

AXI* wite data.

axi_taget_wlast 1 Output

AXI* wite tasactio last data tasfe. Idicates whethe the cuet tasfe is the last data tasfe i a wite tasactio.

axi_taget_weady 1 Iput

AXI* eady sigal fo wite data. Idicates that a wite data chael tasfe ca be accepted.

axi_taget_wvalid 1 Output

AXI* valid sigal fo wite data. Idicates that a wite data chael sigals ae valid.

axi_taget_wstb 8 Output

AXI* wite stobes. Idicates the byte lae holdig valid data.

AXI Maage Wite Respose Chael Sigals
axi_taget_bid 4 Iput AXI* idetificatio tag fo wite espose.
axi_taget_besp 2 Iput

AXI* wite espose. Idicates wite espose status.

axi_taget_bvalid 1 Iput

AXI* valid sigal fo wite espose. Idicates that the wite espose chael sigals ae valid.

axi_taget_beady 1 Output

AXI* eady sigal fo wite espose. Idicates that the wite espose chael tasfe ca be accepted.

AXI Maage Read Data Chael Sigals
axi_taget_data 64 Iput

AXI* ead data.

axi_taget_esp 2 Iput

AXI* ead espose. Idicates ead tasfe status.

axi_taget_last 1 Iput

AXI* ead tasactio last data tasfe. Idicates whethe the cuet tasfe is the last data tasfe i a ead tasactio.

axi_taget_eady 1 Output

AXI* ead data chael eady sigal. Idicates that a tasfe o the ead data chael ca be accepted.

axi_taget_valid 1 Iput

AXI* valid sigal fo ead data chael. Idicates that the ead data chael sigals ae valid.

axi_taget_id 4 Iput AXI* idetificatio tag fo ead data ad espose.
AXI Maage Read Respose Chael Sigals
axi_taget_aid 4 Output

AXI* idetificatio tag fo ead addess tasactio.

axi_taget_aadd 32 Output

AXI* addess of the fist tasfe i a ead tasactio.

axi_taget_ale 8 Output

AXI* legth. Idetifies the umbe of data tasfes duig the ead tasactio.

axi_taget_asize 3 Output AXI* size.

Idetifies the umbe of bytes i each data tasfe i a ead tasactio.

axi_taget_abust 2 Output

AXI* bust type. Idicates how addess chages betwee each tasfe i a ead tasactio.

axi_taget_alock 1 Output Povides ifomatio about the atomic chaacteistics of a AXI* ead tasactio.
axi_taget_acache 4 Output Idicates how a ead tasactio is equied to pogess though a system.
axi_taget_apot 3 Output

Potectio attibutes of a ead tasactio: pivilege, secuity level, ad access type.

axi_taget_aqos 4 Output Quality of Sevice idetifie fo a ead tasactio.
axi_taget_avalid 1 Output

AXI* valid sigal fo ead tasactio. Idicates that the ead addess chael sigals ae valid.

axi_taget_ause 5 Output AXI* use-defied extesio fo the ead addess chael.
axi_taget_aeady 1 Iput

AXI* ead addess chael eady sigal. Idicates that a tasfe o the ead addess chael ca be accepted.

Level Two Title