Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.6.3. Error Code Recovery

The table below descibes possible steps to ecove fom a eo code. Eo ecovey depeds o specific use case.
Table 15.  Eo Code Recovey fo Kow Eo Codes
Value Eo Code Respose Eo Code Recovey
4 INVALID_COMMAND_PARAMETERS Resed the commad heade o heade with agumets with coected paametes.

Fo example, esue that the legth field settig i heade is set with the coect value.
6 COMMAND_INVALID_ON_SOURCE Resed the commad fom valid souce such as JTAG, HPS, o coe fabic.
8 CLIENT_ID_NO_MATCH Wait fo the cliet who opeed the access to quad SPI to complete its access ad the closes the exclusive access to quad SPI.
9 INVALID_ADDRESS

Possible eo ecovey steps:

Fo GET_VOLTAGE commad: Sed commad with a valid bitmask.

Fo GET_TEMPERATURE commad: Sed commad with valid seso locatio ad seso mask.

Fo QSPI opeatio:
  • Sed commad with a valid chip select.
  • Sed commad with a valid QSPI flash addess.

Fo RSU: Sed commad with a valid stat addess of the factoy image o applicatio.

B TIMEOUT

Possible ecovey steps:

Fo GET_TEMPERATURE commad: Rety to sed the commad agai. If poblem pesists, ecofigue o powe cycle the device.

Fo QSPI opeatio: Check sigal itegity of QSPI itefaces ad attempt commad agai.

Fo HPS estat opeatio: Rety to sed the commad agai.
C HW_NOT_READY

Possible ecovey steps:

Fo QSPI opeatio:
  • Recofigue the device via souce.
  • Esue that IP used to build you desig allows access to the QSPI flash.
  • Check fo QSPI_SET_CS commads afte evey QSPI_OPEN equest.

Fo RSU: Cofigue the device with RSU image.
80 QSPI_HW_ERROR Check the QSPI iteface sigal itegity ad esue the QSPI device is ot damaged.
81 QSPI_ALREADY_OPEN Cliet aleady opeed QSPI. Cotiue with the ext opeatio.
82 EFUSE_SYSTEM_FAILURE Attempt ecofiguatio o powe cycle. If eo pesists afte ecofiguatio o powe cycle, the device may be damaged ad uecoveable.
100 NOT_CONFIGURED Sed a bitsteam that cofigues the HPS.
1FF ALT_SDM_MBOX_RESP_DEVICE_ BUSY

Possible eo ecovey steps:

Fo QSPI opeatio: Wait fo ogoig cofiguatio o othe cliet to complete opeatio.

Fo RSU: Recofigue device to ecove fom iteal eo.

Fo HPS estat opeatio: Wait fo ecofiguatio via HPS o HPS Cold Reset to complete.

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