Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.6.2. Error Code Responses

Table 14.  Eo Codes
Value (Hex) Eo Code Respose Desciptio
0 OK

Idicates that the commad completed successfully.

A commad may eoeously etu the OK status if a commad, such as QSPI_READ is patially successful.

1 INVALID_COMMAND Idicates that the cuetly loaded boot ROM caot decode o ecogize the commad code.
3 UNKNOWN_COMMAND Idicates that the cuetly loaded fimwae caot decode the commad code.
4 INVALID_COMMAND_PARAMETERS Idicates that the commad is icoectly fomatted. Fo example, the legth field settig i heade is ot valid.
6 COMMAND_INVALID_ON_SOURCE Idicates that the commad is fom a souce fo which it is ot eabled.
8 CLIENT_ID_NO_MATCH Idicates that the Cliet ID caot complete the equest to close the exclusive access to quad SPI. The Cliet ID does ot match the existig cliet with the cuet exclusive access to quad SPI.
9 INVALID_ADDRESS The addess is ivalid. This eo idicates oe of the followig coditios:
  • A ualiged addess
  • A addess age poblem
  • A ead pemissio poblem
  • A ivalid chip select value, displayig value of moe tha 3
  • A ivalid addess i RSU case
  • A ivalid bitmask value fo GET_VOLTAGE commad
  • A ivalid page selectio fo GET_TEMPERATURE commad
A AUTHENTICATION_FAIL Idicates the cofiguatio bitsteam sigatue autheticatio failue.
B TIMEOUT This eo idicates time out due to the followig coditios:
  • Commad
  • Waitig fo QSPI_READ opeatio to complete
  • Waitig fo the equested tempeatue eadig fom oe of the tempeatue sesos. May idicate a potetial hadwae eo i the tempeatue seso.
C HW_NOT_READY Idicates oe of the followig coditios:
  • The hadwae is ot eady. Ca idicate eithe a iitializatio o cofiguatio poblem. The hadwae may efe to quad SPI.
  • RSU image is ot used to cofigue the FPGA.
  • RSU image is ot used to cofigue the eASIC.
D HW_ERROR Idicates that the commad completed usuccessfully due to uecoveable hadwae eo.
80 - 8F COMMAND_SPECIFIC_ERROR Idicates a commad specific eo due to a SDM commad you used.
SDM Commad Eo Name Eo code Desciptio
GET_CHIPID EFUSE_SYSTEM_FAILURE 0x82 Idicates that the eFuse cache poite is ivalid.

QSPI_OPEN/

QSPI_CLOSE/

QSPI_SET_CS/

QSPI_READ_DEVICE_REG/

QSPI_WRITE_DEVICE_REG/

QSPI_SEND_DEVICE_OP/

QSPI_READ

QSPI_HW_ERROR 0x80 Idicates QSPI flash memoy eo. This eo idicates oe of the followig coditios:
  • A QSPI flash chip select settig poblem
  • A QSPI flash iitializatio poblem
  • A QSPI flash esettig poblem
  • A QSPI flash settigs update poblem
QSPI_ALREADY_OPEN 0x81 Idicates that the cliet's exclusive access to QSPI flash via QSPI_OPEN commad is aleady ope.
100 NOT_CONFIGURED Idicates that the device is ot cofigued.
1FF ALT_SDM_MBOX_RESP_DEVICE_ BUSY Idicates that the device is busy due to followig use cases:
  • RSU: Fimwae is uable to tasitio to diffeet vesio due to a iteal eo.
  • HPS: HPS is busy whe i HPS ecofiguatio pocess o HPS cold eset.
2FF ALT_SDM_MBOX_RESP_NO_VALID_RESP_AVAILABLE Idicates that thee is o valid espose available.
3FF ALT_SDM_MBOX_RESP_ERROR Geeal Eo.
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