Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.11.2.1. Configuration Parameter

The LibRSU HAL API cofiguatio paametes ae stoed i Boad Suppot Package (BSP) settig file. You ca edit the cofiguatio paametes though the BSP Dive tab. If they ae ot specified, the LibRSU HAL API uses the default value.

Table 27.  Cofiguatio Paamete
Vaiable Default Value Desciptio
su_potected_slot -1 Allows potectio o a cetai slot umbe. Oly slots betwee 0 ad 31 ca be potected by this featue. By default (su_potected_slot = -1), o slot is potected.
su_log_level 3 Allows customizatio o how much loggig ifomatio is displayed. The valid iputs ae 1,2 ad 3. By default, the log level is set as 3 ad all loggig ifomatio is displayed.
eable_spt_checksum Disable Eables check ad maiteace of the SPT checksum. By default, the SPT checksum featue is disabled.
eable_su Disable Eables the RSU fuctios. By default, it is disabled ad the Mailbox Cliet Itel FPGA IP coe pefoms without the RSU fuctios.

fpga_device

  • Statix10
Disable Allows cofiguatio tagetig the selected Itel FPGA devices. By default, the cofiguatio tagets Agilex™ 7 ad Agilex™ 5 devices, thus the Statix® 10 settig is disabled.
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