Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.11.2. LibRSU HAL API

The LibRSU HAL API is available fo this cotolle i the followig softwae files:
  • libsu.h
  • libsu.c
  • su_cliet.h
  • su_cliet.c

The HAL dive implemets the emote system update featue i SDM-based devices which update the Itel FPGA image ad pefom device ecofiguatio emotely. The Nios® II ad Nios® V pocessos act as the emote system update host cotolle thoughout the whole pocess.

It is ecommeded that you system memoy has a miimum stack size o heap size of twice the size of the Decisio Fimwae of the espective SDM-based device.

Note:

You may eed to modify the stig MAILBOX_NAME based o you system.h i the followig souce codes.

  • Fo Statix® 10 ad Agilex™ 7 devices:
    altea_s10_mailbox_cliet_flash_su.c
    altea_s10_mailbox_cliet_su.c
  • Fo Agilex™ 5 devices:
    itel_mailbox_cliet_flash_su.c
    itel_mailbox_cliet_su.c
You eed the ZLIB biaies to use the LibRSU HAL API. The followig code geeates the ZLIB libaies accodig to the specific vesio, ad eames the folde as zlib. It is ecommeded to use the latest vesio of ZLIB biaies, povided i the zlib.et Home Page. 
wget http://zlib.et/zlib-<vesio>.ta.gz 
ta xf zlib-<vesio>.ta.gz 
mv zlib-<vesio> zlib

The fial diectoy path of the zlib folde must be oe level above the bsp poject folde (this folde cotais the Nios V pocesso Boad Suppot Package) as show i the followig figue.

Figue 6. Diectoy Stuctue

Sectio Cotet
Cofiguatio Paamete
Eo Codes
Usig LibRSU HAL API without Valid SPT o CPB
Data Type
Fuctios
RSU Cliet API

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