The espose icludes a oe-wod agumet fo each bit set i the bitmask. The voltage etued is a usiged fixed-poit umbe with 16 bits below the biay poit. Fo example, a voltage of 0.75V etus 0x0000C000.^{13 14 15}

The GET_TEMPERATURE commad etus the tempeatue o tempeatues of the coe fabic o tasceive chael locatios you specify.

The tempeatue etued is a siged fixed value with 8 bits below the biay poit. Fo example, a tempeatue of 10°C etus 0x00000A00. A of tempeatue -1.5°C etus 0xFFFFFE80.

If the bitmask specifies a ivalid Locatio, the commad etus a eo code which is ay value i the age 0x80000000 -0x800000FF.

Fo Statix® 10 devices: Refe to the Tempeatue Seso Chaels ad Locatios i the Statix® 10 Aalog to Digital Covete Use Guide fo moe ifomatio about seso locatios.

Fo Agilex™ 7 devices: Refe to the Agilex™ 7 Powe Maagemet Use Guide fo moe ifomatio about local build-i tempeatue sesos.

Fo Agilex™ 5 devices: Refe to the Agilex™ 5 Powe Maagemet Use Guide fo moe ifomatio about local build-i tempeatue sesos.

This commad is fo VID-eabled devices ad allows ead of 1 byte ad 2 byte egiste cotets of I2C devices ove the PMBus. Specify the device addess ad egiste addess to ead, as commad paametes.

The FPGA suppots I2C device addess i 7-bit fomat. Two goups of eight addesses (0000 XXX ad 1111 XXX) ae eseved ad ot accessible via Mailbox commad.

The PMBus* Specificatio has defiitios fo egistes i the addess age of 0x00 - 0xAE. Registe defiitios beyod this age ae defied by the I2C device’s maufactue.

Whe successful, etus the OK espose code followed by the ead data fom the device. A failue espose etus a eo code.

Tigges ecofiguatio fom the data souce that ca be eithe the factoy o a applicatio image.

This commad takes a optioal 64-bit agumet that specifies the ecofiguatio data addess i the flash. Whe sedig the agumet to the IP, you fist sed bits [31:0] followed by bits [63:32]. If you do ot povide this agumet its value is assumed to be 0.

• Bit [31:0]: The stat addess of a applicatio image.
• Bit [63:32]: Reseved (wite as 0).

Oce the device pocesses this commad, it etus the espose heade to espose FIFO befoe it poceeds to ecofigue the device. Esue the host PC o host cotolle stops sevicig othe iteupts ad focuses o eadig the espose heade data to idicate the commad completed successfully. Othewise, the host PC o host cotolle may ot be able to eceive the espose oce the ecofiguatio pocess stated.

Oce the device poceeds with ecofiguatio, the lik betwee the exteal host ad FPGA is lost. If you use PCIe* i you desig, you eed to e-eumeate the PCIe* lik.

RSU_GET_SPT etieves the quad SPI flash locatio fo the two sub-patitio tables that the RSU uses: SPT0 ad SPT1.

The 4-wod espose cotais the followig ifomatio:

Repots the status of the last ecofiguatio. You ca use this commad to check the cofiguatio status duig ad afte cofiguatio. The espose cotais the followig ifomatio:

Descibes the most ecet cofiguatio elated eo. Retus 0 whe thee ae o cofiguatio eos.

Refe to Appedix: CONFIG_STATUS ad RSU_STATUS Eo Code Desciptios i the Mailbox Cliet Itel® FPGA IP Use Guide fo moe ifomatio.

• Bit [31]: Cuet STATUS output value (active low)
• Bit [30]: Detected CONFIG iput value (active low)
• Bit [29:8]: Reseved
• Bit [7:6]: Cofiguatio clock souce
  • 01 = Iteal oscillato
  • 10 = OSC_CLK_1
  • 11 = Secue PLL
  Note: Bit [7:6] is oly applicable to Agilex™ 7 ad Agilex™ 5 devices
• Bit [5]: Reseved
• Bit [4]: VID Eabled
• Bit [3]: Reseved
• Bit [2:0]: The MSEL value at powe up

• Bit [31:6]: Reseved
• Bit [5]: HPS_WARMRESET
• Bit [4]: HPS_COLDRESET
• Bit [3]: SEU_ERROR
• Bit [2]: CVP_DONE
• Bit [1]: INIT_DONE
• Bit [0]: CONF_DONE

Eo Details

Flash offset of the highest pioity failig applicatio image. If multiple images ae available i flash memoy, stoes the value of the fist image that failed. A value of all 0s idicates o failig images. If thee ae o failig images, the emaide of the emaiig wods of the status ifomatio do ot stoe valid ifomatio.

Retus 0 fo o failues. Refe to Appedix: CONFIG_STATUS ad RSU_STATUS Eo Code Desciptios i the Mailbox Cliet Itel® FPGA IP Use Guide fo moe ifomatio.

RSU iteface vesio ad eo souce.

Fo moe ifomatio, efe to the RSU Status ad Eo Codes sectio i the Had Pocesso System Remote System Update Use Guide.

Cout of the umbe of eties that have bee attempted fo the cuet image. The coute is 0 iitially. The coute is set to 1 afte the fist ety, the 2 afte a secod ety.

Specify the maximum umbe of eties i you Quatus® Pime Settigs File (.qsf). The commad is: set_global_assigmet -ame RSU_MAX_RETRY_COUNT 3. Valid values fo the MAX_RETRY coute ae 1-3. The actual umbe of available eties is MAX_RETRY -1

This field was added i vesio 19.3 of the Quatus® Pime Po Editio softwae.

This commad is ot available befoe vesio 19.3 of the Quatus® Pime Po Editio softwae.

Requests exclusive access to the quad SPI. You issue this equest befoe ay othe QSPI equests. The SDM accepts the equest if the quad SPI is ot i use ad the SDM is ot cofiguig the device. Retus the OK espose code if the SDM gats access. Upo eceivig the OK espose code, issue the QSPI_SET_CS commad to select the flash devices.

The SDM gats exclusive access to the cliet usig this mailbox. Othe cliets caot access the quad SPI util the active cliet eliquishes access usig the QSPI_CLOSE commad.

Access to the QSPI flash memoy devices usig SDM_IO pis is oly available fo the AS x4 cofiguatio scheme, JTAG cofiguatio, ad a desig compiled fo AS x4 cofiguatio. Fo the Avalo® steamig iteface ( Avalo® ST) cofiguatio scheme, you must coect QSPI flash memoies to GPIO pis.

Access to the quad SPI flash memoy devices via ay mailbox cliet IP is ot available by default i desigs that iclude the HPS, uless you disable the QSPI i HPS softwae cofiguatio.

• Bits[31:28]: Flash device to select. Refe to the ifomatio below fo the value that coespods to the CSO[0:3] pis.
  • Value 4'h0000 selects the flash that coespods to CSO[0]
  • Value 4'h0001 selects the flash that coespods to CSO[1]
  • Value 4'h0002 selects the flash that coespods to CSO[2]
  • Value 4'h0003 selects the flash that coespods to CSO[3]
• Bits[27:0]: Reseved (wite as 0).

Fo Statix® 10 devices: Duig AS x4 cofiguatio scheme, this commad is optioal. The chip select lie follows the last executed QSPI_SET_CS commad o defaults to CSO[0] afte the AS x4 cofiguatio.

Fo Agilex™ 7 ad Agilex™ 5 devices: Duig AS x4 cofiguatio scheme, this commad is equied afte evey QSPI_OPEN commad.

Fo all devices duig JTAG cofiguatio scheme, this commad is equied afte evey QSPI_OPEN commad.

Reads the attached quad SPI device. The maximum tasfe size is 4 kilobytes (KB) o 1024 wods.

Fo a patially successful ead, QSPI_READ may eoeously etu the OK status.

Wites data to the quad SPI device. The maximum tasfe size is 4 kilobytes (KB) o 1024 wods.

To pepae memoy fo wites, use the QSPI_ERASE commad befoe issuig this commad.

• The flash addess offset to stat the ease (oe wod). Depedig o the umbe of wods to ease, the stat addess must be:
  • 4 KB aliged if umbe wods to ease is 0x400
  • 32 KB aliged if umbe wods to ease is 0x2000
  • 64 KB aliged if umbe wods to ease is 0x4000
  Retus a eo fo o-4/32/64 KB aliged addesses.
• The umbe of wods to ease is specified i multiples of:
  • 0x400 to ease 4 KB (1024 wods) of data. This optio is the miimum ease size.
  • 0x2000 to ease 32 KB (8192 wods) of data
  • 0x4000 to ease 64 KB (16384 wods) of data

• The opcode fo the ead commad.
• The umbe of bytes to ead.

A successful ead etus the OK espose code followed by the data ead fom the device. The ead data etu is i multiple of 4 bytes. If the bytes to ead is ot a exact multiple of 4 bytes, it is padded with multiple of 4 bytes util the ext wod bouday ad the padded bit value is zeo.

• The opcode fo the wite commad.
• The umbe of bytes to wite.
• The data to wite.

To pefom a secto ease o sub-secto ease, you must specify the seial flash addess i most sigificat byte (MSB) to least sigificat byte (LSB) ode as the followig example illustates.

To ease a secto of a Mico* 2 gigabit (Gb) flash at addess 0x04FF0000 usig the QSPI_WRITE_DEVICE_REG commad, wite the flash addess i MSB to LSB ode as show hee:

Heade: 0x00003036

Opcode: 0x000000DC

Numbe of bytes to wite: 0x00000004

Flash addess: 0x0000FF04

A successful wite etus the OK espose code. This commad pads data that is ot a multiple of 4 bytes to the ext wod bouday. The commad pads the data with zeo.

• The opcode to sed the quad SPI device.

A successful commad etus the OK espose code.

This commad takes two 32-bit wods as agumets.

Wod 0:

• Bits [1:0]: SHA Vaiat. This paamete detemies the type of SHA algoithm used. It ca take the followig values:
  • 00: SHA512
  • 01: SHA384
  • 10: SHA256
• Bits[31:2]: Stat Addess. This is the addess i flash to stat veifyig fom. The addess must be 4 bytes aliged.

Wod 1:

• Bits [31:0]: NumBytes. This epesets the umbe of bytes to be used i the SHA ead. Must be a multiple of 64.

Typically, cofiguatio cycle cout is captued i the lowe 32 bits. It is ulikely that the fimwae etus a 64-bit cycle cout. If this happes, you must cocateate the two 32-bit wods to obtai the total cycle cout value.

Example:

Retued espose: 0x007C27EE = 8136686 cycles

Cofiguatio cotol clock fequecy: 200 MHz

Cofiguatio time: (8136686/200000000) × 1000 = 40.68 ms

• 1 if Eo Message Queue is empty; else
• Legth +2, up to FIFO size[17]

Whe a SEU eo is detected, the eo ifomatio is stoed i the eo message queue. This commad povides a way to ispect the queue ad emove eties fom it.

Whe you set the SEU_ERROR pi i the Device ad Pi Optios widow, you may obseve that the SEU_ERROR sigal emais high whe thee is oe o moe eos i the eo message queue. The sigal goes low whe the eo message queue is empty.

The espose is oe wod log whe thee ae o eos i the eo message queue.

Whe thee is oe o moe eos i the queue, the fist eo fom the queue is emoved ad etued i the subsequet wods. This commad etus oe elemet fom the queue at a time.

This commad epots the SEU statistics fo a give secto.

This commad takes oe 32-bit wods as agumets.

Wod 0:

• Bit [31:24]: Reseved (wite as 0)
• Bit [23:16]: Secto Addess
• Bit [15:0]: Reseved (wite as 0)

The espose legth as show below:

• Wod 0:

  • Bit [31:0]:T_seu_cycle

• Wod 1:
  • Bit [31:0]:T_seu_detect
• Wod 2:
  • Bit [31:0]:T_seu_coect
• Wod 3:
  • Bit [31:0]:T_seu_iject_detect
• Wod 4:
  • Bit [31:0]:T_sdm_seu_poll_iteval
• Wod 5: Bit
  • [31:0]:T_sdm_seu_pi_toggle_ovehead

Time (secod) = cycle/iteal clock fequecy

Refe to the espective SEU Mitigatio Use Guide fo moe ifomatio.

If detectio is wokig, the the device coects this eo if possible ad epots it back to the use though the stadad SEU epotig mechaism.

Ijectio may oly taget to a pe-defied list of locatio fo uused CRAMs ae povided (idetified by CRAM_SEL 0 to 7).

Example:

Refe to the espective SEU Mitigatio Use Guide fo moe ifomatio.

This commad isets a ECC eo ito selected RAM of CNT/SDM ad tigge ECC eo by pefomig a eadback. Use ca oly iset sigle bit ECC.

This commad takes two 32-bit wods as agumets.

Wod 0:

• Bits [1:0]: SHA Vaiat. Etes 00 fo SHA512 algoithm
• Bits[31:2]: Stat Addess. This is the addess i flash to stat veifyig fom. The addess must be 4 bytes aliged.

Wod 1:

• Bits[31:0]: NumBytes. This epesets the umbe of bytes to be used i the SHA ead. Must be a multiple of 64.

The espose legth etus 16 wods.

Povides a iteface fo Powe Maagemet Fimwae (PMF) ad Voltage Regulato (VR) data. This commad is fo VID-eabled devices with both VR pollig ad PMF also eabled.

This commad is available i the Quatus® Pime Po Editio softwae vesio 23.3 o late.