SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.8.10.1. Retry-on-Error

The retry-on-error mechanism improves the bit error rate of your data.
The retry-on-error parameter provides for segments with errors to be retransmitted, so that only good segments are delivered to the Atlantic receive interface. When you turn on the Retry-on-error parameter, all segments sent by the transmitter are acknowledged.
  • ACK: The received segment is good and error-free.
  • NACK: The received segment contains an error.
    • If you turn on the Retry-on-error parameter, the transmitter retransmits all segments starting from the segment with errors.
    • If you turn off the Retry-on-error parameter, the receiver raises a data error.

The segment buffers in the transmitting logic hold segments until they have been acknowledged. Once a segment has been acknowledged by ACK, it is released from the buffer so that the buffer can be used for another segment. If a segment is acknowledged by NACK, that segment and all segments sent after that segment are retransmitted.

The IP core can hold up to seven segments waiting for acknowledgement at once. If more segments arrive while all eight buffers are occupied, the priority data port stalls until an acknowledgment is received, freeing up a buffer for the next segment.

The retry-on-error operation proceeds in this sequence:
  1. When the receiver receives a good segment, the segment is delivered to the Atlantic interface and an ACK acknowledgment is sent back to the transmitter.
  2. Any data errors cause the segment to be acknowledged as errored (NACK). Once that happens, the receiver ignores all incoming data until it receives the retransmitted segment.
  3. All segments are numbered internally with a segment ID. The receiver knows which segment it expects next, so if the next expected segment has been corrupted or lost, the next received segment has the wrong segment number and the receiver requests a retransmission of the sequence starting with the segment ID it was expecting.
  4. The oldest outstanding segment to be acknowledged has an associated timer, set by the Timeout value on the Link Layer page in the SerialLite II parameter editor. If an acknowledgment (ACK or NACK) is lost or corrupted in transit, the timer expires causing the affected segment and all subsequent segments to be retransmitted.
  5. The transmitter knows which segment it expects to be acknowledged next. If the next acknowledgment is not for the expected segment, the transmitter infers that the expected acknowledgment was lost and retransmits the segment in question and all subsequent segments. Only segments that have the correct segment ID are buffered. The timer starts when the segment is identified as the next segment to be acknowledged.
  6. If the timer expires three times in succession, a link error is declared and the link is restarted. You can control the Timeout limit in the SerialLite II parameter editor.
    • Do not to set the time out to be too long so the system does not have to wait too long for such situations to resolve.
    • Do not set the time out to be too short because then the system always times out and the link never remains up.

Implementation of the retry-on-error mechanism is optional for the priority port. If the Retry-on-error parameter is turned off, no segment acknowledgments are generated or expected, and all segments are transmitted without any acknowledgments from the receiver.

Table 11.  Retry-on-Error ResponsesThis table summarizes the response to various transmission errors.
Error Response
Invalid 8B/10B codes groups Far end transmitter issues NACK
Running disparity errors Far end transmitter issues NACK
Unsupported valid code groups Far end transmitter issues NACK
CRC errored segments with {EGP} sequence Far end transmitter issues NACK
Out of order segment Far end transmitter issues NACK
Out of order acknowledgment Near end transmitter starts resend
Figure 13. Retry-On-Error ExampleThis figure shows an example of the retry-on-error operation.
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