SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.8. SerialLite II Parameter Settings

You set the parameters using the SerialLite II parameter editor.
Table 6.  SerialLite II Parameters

Parameter

Description

Physical Layer

Device family
Select the targeted device family.
Note: For Intel® Arria® 10 devices, contact your local Intel representative or file a Service Request (SR).

Data rate

Key in a data rate in megabits per second (Mbps). The SerialLite II IP core supports data rates of 622 to 6,375 Mbps per lane.

Note: The data rate must be an acceptable range for the Transfer size. The parameter editor returns a warning or an error message if you specify a data rate that is not within the range for the specified Transfer size.

Transfer size

The Transfer size (TSIZE) parameter determines the number of contiguous data columns and the internal data path width per lane.
  • TSIZE 1— equates to an internal data path of 8 bits (Recommended for less than 2.5 gigabits per second (Gbps))
  • TSIZE 2 —equates to an internal data path of 16 bits (Recommended for less than or equal to 3.125 Gbps)
  • TSIZE 4 —equates to an internal data path of 32 bits (Typically for greater than 3.125 Gbps, and only available for Arria V, Cyclone V, Stratix IV, and Stratix V devices)
A transfer size also determines the width of the SERDES block:
  • TSIZE 1—10 bit-wide SERDES block
  • TSIZE 2—20 bit-wide SERDES block
  • TSIZE 4—40 bit-wide SERDES block

Reference clock frequency

This option defines the frequency of the reference clock for the Arria II GX or Stratix IV internal transceiver. You can select any frequency supported by the transceiver.
Note: If you select a reference clock frequency that is not equal to the data rate/(transfer size) * 10, this option is disabled if you turned on the Receiver only port type option.

Port type

Select a port type: Bidirectional, Transmitter only, or Receiver only.

Note: If you choose Transmitter only or Receiver only, the self-synchronized link-up parameter (LSM) is enabled by default.

Self-synchronized link-up

This parameter allows the receiver on the far end of the link to synchronize itself to incoming data streams, rather than on an exchange of status information with the transmitter.

Note: This feature is only for single lane applications.

Number of lanes (Transmitter and Receiver settings)

Select the number of lanes for the transmitter and receiver. This parameter dictates the number of serial links, essentially the number of external inputs and outputs (I/Os) for the IP core. Because each lane operates at the bit rate, you can increase the bandwidth by adding lanes.
Note: If adding a lane provides more bandwidth than needed, you can reduce the system clock rate, thereby mitigating possible high-speed design issues and making it easier to meet performance.

Scramble

Turn on to scramble the data. Scrambling the data eliminates repeating characters that affect the EMI substantially at high data rates. This parameter applies only to the transmitter, and allows for scrambling (like CRC) to be enabled in one direction only, as required.

Scrambling is recommended for data rates greater than 3,125 Mbps, and is optional for lower data rates (622 to 3,125 Mbps).

De-scramble

Turn to to descramble the data. This parameter applies only to the receiver, and allows for descrambling (like CRC) to be enabled in one direction only, as required.

Descrambling is required if the incoming data stream is scrambled.

Broadcast mode

Turn on to use broadcast mode. This parameter applies only to the transmitter.

If you enable this parameter, you configure the IP core to use a single shared transmitter and multiple receivers in the master device.

Enable frequency offset tolerance

This parameter sets the value for the frequency offset tolerance (clock compensation). This parameter also determines whether the system is configured for synchronous or asynchronous clocking operation.

If you turn on this option, select an offset tolerance of ±100 or ±300 parts per million (ppm).

Link Layer

Data type

Select whether to format the data as a stream or in packets. If you select Streaming, all link layer basic parameters, including data and priority ports, and buffering are disabled (grayed out). Streaming mode does not include link-layer functions.

Packet type

Select whether to send your packets as priority packets, data packets, or both.

Enable flow control

The SerialLite II IP core provides this parameter as an optional means of exerting backpressure on a data source when data consumption is too slow. Turn on this parameter to ensure that the receive FIFO buffers do not overflow.

Note: Flow control is only needed when the system logic on the receiving end of the link is reading the data slower than the system logic on the transmitting end of the link is sending data.
Pause quantum time Activation of flow control causes a pause in transmission. Specify a pause duration from to 8 to 2,040 columns.
Threshold You must set the Threshold parameter to a value such that the FIFO does not completely empty during a flow control operation (this can cause inefficiencies in the system), and leave enough room in the FIFO to ensure any remaining data in the system can be safely stored in the FIFO without the FIFO overflowing
Refresh period The flow control refresh period determines the number of columns before a flow control packet can be retransmitted (for example if a flow control link management packet is lost or corrupted). This period must be less than the pause quantum time. The packet is retransmitted if the FIFO buffer is still breached.
Retry-on-error
This parameter improves the bit error rate of your data.
  • On: Logic is created to acknowledge segments and retransmit segments when errors occur. Eight transmit segment buffers are created.
  • Off: Logic is not created to acknowledge segments. This is the default setting.

If you turn off this parameter, no segment acknowledgments are generated or expected, and all segments are transmitted without any acknowledgments from the receiver.

This parameter is only available for priority packets.
Timeout Set the time out value for the segment to be acknowledged. The time-out value is based primarily on the round trip latency—from the time a packet is sent to when the acknowledge signal is returned to that transmitter. The exact value of the round trip latency is undetermined, pending device characterization, but a value of 1,024 columns is recommended.
  • Do not to set the time out to be too long so the system does not have to wait too long for link errors to resolve.
  • Do not set the time out to be too short because then the system always times out and the link never remains up.
Segment size

This parameter is only applicable when the Retry-on-error parameter is turned on. This parameter settings range from 8 to 2,048 bytes in 2n increments, and the default value is 256 bytes.

Priority packets are broken into segments of segment size bytes and sent across the link. Priority packets less than or equal to segment size bytes and without an end marker are buffered before transmission. This buffering is required to support the Retry-on-error option, which is only allowed for priority packets.

If a packet is larger than a segment size, a full segment must be queued before it can be transmitted. This queuing may result in mid-packet backpressure on the priority port Atlantic interface. Segment interleaving, priority segments destined for different ports, is fully supported, as long as the address change occurs on a segment boundary.

Buffer size (Transmitter and Receiver)

Specify a FIFO buffer size value for the transmitter and receiver.

Enable CRC for priority/data packets (Transmitter and Receiver)

If your transmitter or receiver requires cyclic redundancy code (CRC) checking, turn on the Enable CRC option for your chosen packet type.
  • On: CRC logic is created. CRC usage is specified independently for each port.
  • Off: CRC logic is not created. CRC usage is specified independently for each port. This is the default CRC setting.

CRC Type
Select 16 bits or 32 bits for the CRC type.
  • 16 bits: Generates a two-byte CRC. Adequate for packets of around 1 KBytes or smaller. This is the default algorithm when CRC is enabled.
  • 32 bits: Generates a 4-byte CRC. Should only be used for packets larger than about 1 KBytes or when extreme protection is required, because it is resource-intensive.
Configure Transceiver (only applicable for Arria II GX and Stratix IV devices)

Specify VOD control setting
Select the Voltage Output Differential (VOD) control setting value.
Note: This parameter is disabled when the number of lanes in the transmit direction is equal to zero.

Specify pre-emphasis control setting

Select pre-emphasis control setting value.

For Stratix IV devices, the pre-emphasis control values supported are 0,1,2,3,4, and 5.
  • 0 = Pre-emphasis option is turned off
  • 1 = Maximum negative value
  • 2 = Medium negative value
  • 3 = Special value in which only the first post-tap is set (set to the maximum), while the other taps are off
  • 4 = Medium positive value
  • 5 = Maximum positive value

For Arria II GX devices, the pre-emphasis setting cannot be changed.

This parameter is set to 0 by default. It is disabled when the number of lanes in the transmit direction is equal to zero.

Bandwidth mode (Transmitter and Receiver)

The transmitter and receiver PLLs in the ALTGX IP core offer programmable bandwidth settings. The PLL bandwidth is the measure of its ability to track the input clock and jitter, determined by the -3 dB frequency of the PLL’s closed-loop gain.

Select low or high bandwidth mode for the transmitter and low, medium, or high bandwidth mode for the receiver.
  • The low bandwidth setting filters out more high frequency input clock jitter, but increases lock time. The PLL is set to the low setting by default.
  • The medium setting balances the lock time and noise rejection/jitter filtering between the high and low settings.
  • The high bandwidth setting provides a faster lock time and tracks more jitter on the input clock source which passes it through the PLL to help reject noise from the voltage control oscillator (VCO) and power supplies.

If the number of lanes in the transmit or receive direction is equal to zero, the bandwidth mode for that direction is disabled.

Note: This parameter is not applicable for Arria II GX devices.

Transmitter buffer power (VCCH)
This setting is used to calculate the VOD from the buffer power supply and the transmitter termination to derive the proper VOD range.
  • Arria II GX devices = 1.5 V
  • Stratix IV devices = 1.4 V or 1.5 V

Specify equalizer control setting

Select the equalizer control setting value.

The transceiver offers an equalization circuit in each receiver channel to increase noise margins and help reduce the effects of high frequency losses. The programmable equalizer compensates for inter-symbol interference (ISI) and high frequency losses that distort the signal and reduce the noise margin of the transmission medium by equalizing the frequency response.

For Stratix IV devices, the equalization control values supported are 0, 1, 2, 3, and 4. These values correspond to lowest/off (0), between medium and lowest (1), medium (2), between medium and high (3), and high (4).

For Arria II GX devices, the equalization cannot be changed.

Starting channel number
To reconfigure the functionality settings, select a starting channel number. The range for the dynamic reconfiguration starting channel number setting is 0 to 380. These ranges are in multiples of four because the dynamic reconfiguration interface is per transceiver block. The range 0 to 380 is the logical channel address, based purely on the number of possible transceiver instances.
Note: This parameter is not applicable for Arria II GX devices.

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