Visible to Intel only — GUID: vgo1460616350703
Ixiasoft
Visible to Intel only — GUID: vgo1460616350703
Ixiasoft
4.4. Testbench Components
DUT | The Verilog HDL or VHDL IP functional simulation model of the device under test (DUT) |
SISTER | A Verilog HDL or VHDL IP functional simulation model used to test the DUT. When the DUT is asymmetric (for example, the number of receiving lanes is different than the number of transmitting lanes), is configured in single mode (receiver or transmitter only), or is configured in broadcast mode, the SISTER parameters may not match the DUT parameters, or multiple SISTER MegaCore functions may need to be instantiated. |
AGEN | This testbench includes separate versions of the AGEN module for Verilog HDL and VHDL. |
AMON | This testbench includes separate versions of the AMON module for Verilog HDL and VHDL. |
Status Monitors (pin_mon) | The simulation includes status pin monitors for the DUT and SISTERs (pin_mon_<pin_name>). When enabled (by default), the status monitor compares the received data against the expected data. If the expected value is different from the current value, the monitor flags an error. Set the en input pin high to enable a pin monitor, low to disable a pin monitor, or for Verilog HDL only use the tasks. The Verilog HDL pin monitor expected value can be set by a task. |
Clock and Reset Generator | The DUT and the SISTER use a common clock, with the frequency set by the MegaWizard Plug-In Manager. There is one master reset signal (reset_n) that resets all the logic in the demonstration testbench (DUT, SISTER(s), AGENs, AMONs and status monitors). |
Custom PHY IP Core | The DUT and the SISTER use an external transceiver for Arria V and Stratix V configurations. You are required to separately instantiate the Custom PHY IP core using the MegaWizard Plug-In Manager. |