SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores

The parameters associated with the transceiver configuration in the SerialLite II IP core are disabled because there is no hard transceiver in this configuration. Other parameters for the SerialLite II IP core remains the same and are enabled.

Refer to SerialLite II Parameter Settings for a more detailed description of the parameters.

Table 22.  Custom PHY IP Core SettingsThis table lists the options that you can set using the Custom PHY IP core parameter editor. Note that the required ports are essential for the Custom PHY IP core instantiation.
Option Description Setting
pll_locked output port Provides Tx PLL locking status in the Custom PHY IP core. Optional
tx_ready output port Indicates that the Custom PHY IP core is ready to transmit data. Required
rx_ready output port Indicates that the Custom PHY IP core is ready to receive data. Required
Enable TX Bitslip Provides control for bitslip functionality. Off
Create rx_coreclkin port Provides transceiver clock output to the rx_coreclk signal in the SerialLite II IP core. For Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V designs with more than 1 channel, connect transceiver PHY rx_clkout(0) to rx_coreclkin(N-1:0). Required
Create tx_coreclkin port Provides transceiver clock output to the tx_coreclk signal in the SerialLite II IP core. For Arria® V, Cyclone® V, and Stratix® V designs with more than 1 channel, connect transceiver PHY tx_clkout(0) to tx_coreclkin(N-1:0). Required
Create rx_recovered_clk port Provides a recovered clock output for the transceiver. Off
Create ports Provide the following ports:
  • rx_is_lockedtoref
  • rx_is_lockedtodata
  • rx_signaldetect
  • tx_forceelecidle
Optional
Avalon® data interfaces Enables support for Avalon® streaming interface. Optional
Enable embedded reset controller Enables the controller to reset the transceiver. Required
Create word aligner status ports Provide the following ports:
  • rx_syncstatus
  • rx_patterndetect
  • rx_bitslipboundaryselectout
Required
Enable run length violation checking Enables run length violation check to the err_rr_rlv signal in the SerialLite II IP core.
Note: The err_rr_rlv signal is no longer exposed at the top level in the SerialLite II IP core for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices. Enable and monitor this signal from the transceiver.
Required
Enable rate match FIFO Enables support for rate match FIFO. Optional
Create optional rate match FIFO status ports Enable the status ports for rate match FIFO. Optional
Enable 8B/10B encoder/decoder Provide the following ports:
  • rx_runningdisp
  • rx_datak (indicates whether the rx_parallel_data output port contains data or control symbol)
Required
Enable manual disparity control Enables manual disparity control for the 8B/10B encoder/decoder. Off
Create 8B/10B status ports Provide the following status ports for the 8B/10B encoder/decoder operation:
  • rx_errdetect
  • rx_disperr (provides running disparity status to the err_rr_disp signal in the SerialLite II IP core)
Required
Enable byte ordering block Enables byte ordering pattern configuration. Off
Enable byte ordering block manual control Provides manual control for the byte ordering block. Off
Allow PLL/CDR reconfiguration Enables support for dynamic reconfiguration of Tx PLL and Rx CDR. Off
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