SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.8.12. Transmit/Receive FIFO Buffers

The SerialLite II IP core automatically sets the width of the receive FIFO buffers at TSIZE bytes per lane.
  • The transmit FIFO buffers are used by the transmitting end of the SerialLite II link to store data to be transmitted across the high-speed serial link.
  • The receive FIFO buffers are used by the receiving end of the SerialLite II link to store data for presentation to the Atlantic interface and eventual consumption by the system logic.
The size of the FIFO buffers are affected by these factors:
  • Flow control—If flow control is enabled, the FIFO buffer size should change to account for the thresholds that must be set.
  • Pause duration—When optimizing against starvation during flow control, the pause duration affects the FIFO buffer size.
  • Number of packets (and packet sizes)—If you want to use a store-and-forward FIFO (using the eop_dav and a high threshold), the FIFO must be big enough to hold a full packet at minimum.
  • Wire delay and bit rate—The wire propagation delay and the bit rate change the wire latency, which must be accommodated if flow control is used.
Figure 16. Atlantic FIFO Buffer Structure
The FIFO buffer threshold low (FTL), ctl_rxrdp_ftl/ctl_rxhpp_ftl, value for receiver variations controls when the rxrdp_dav/rxhpp_dav signals are asserted for the read side of the FIFO buffer, respectively. If the fill level of the buffer is higher than the FTL value, the rxrdp_dav/rxhpp_dav signal is asserted indicating that there is a burst of data available.
Note: There is no requirement to wait for the rxrdp_dav/rxhpp_dav signal to be asserted; you can read from the buffer at any time by asserting the rxrdp_ena/rxhpp_ena signal at all times and qualifying the data with the rxrdp_val/rxhpp_val signal. The FIFO buffer has built-in underflow protection, such that an underflow condition does not exit.

The receiver Atlantic FIFO buffers include an end-of-packet based data available feature which can be turned on by asserting the ctl_rxrdp_eopdav/ctl_rxhpp_eopdav signals. The end-of-packet feature determines whether the dav remains high: if the signal is asserted, and there is an end-of- packet beneath the FTL threshed, the dav signal remains high until the end-of-packet is read out of the FIFO buffer. Otherwise, if the signal is not asserted, the dav signal only remains high when the fill level of the buffer is higher than the FTL value.

ctl_rxhpp_fth and ctl_rxrdp_fth are the threshold levels for the high priority and regular data ports on the receiver Atlantic FIFO buffers. When the data fill level is higher than the threshold level set by ctl_rxhpp_fth or ctl_rxrdp_fth, or dav = 1, it means that there a large amount of data ready to be fetched at the FIFO buffer. You must set these threshold levels based on your design requirements, and ensure that the FIFO buffer does not underflow. You may also set the threshold levels to segment size of a priority packet; or to the lowest level so that you can fetch data as soon as it is stored in the FIFO buffer.

You can set ctl_rxhpp_ftl to 1 element unit so that it fetches the data from the RX FIFO buffer as soon as there is data available. If you want to store some data before fetching it, you can raise the threshold level. The FIFO buffer threshold high (ctl_txrdp_fth/ctl_txhpp_fth) value for transmitter variations controls when the txrdp_dav/txhpp_dav signals are asserted and deasserted for the write side of the FIFO buffer, respectively. The txrdp_dav signal indicates when there is room available to write new data into the FIFO buffer, and is asserted when the fill level of the FIFO is less than the FTH setting, and deasserted when the fill level of the FIFO is greater than the FTH.

For example, if FTH is five, and the fill level is four, the txrdp_dav/txhpp_dav signal is high, indicating that the user can write data into the FIFO. If the fill level for this example is six, the txrdp_dav/txhpp_dav signal is low, indicating that the user should stop writing data into the FIFO. ctl_txhpp_fth and ctl_txrdp_fth are the threshold levels for the high priority and regular data ports on the transmitter Atlantic FIFO buffers. When the data fill level at the FIFO buffer is lower than the threshold level set by ctl_txhpp_fth or ctl_txrdp_fth, or dav = 1, it means that there are plenty of spaces available for data to write into the buffer. You must set these threshold levels high so that the user logic knows whenever the FIFO buffer has available spaces for data buffering and to ensure that overflow does not occur. However, these threshold settings should not exceed the FIFO depth.

For example, if the transmitter buffer size is 4,096 bytes, and the transmitter FIFO depth is 2,048 element units, you should set the level of ctl_txhpp_fth = 250 element units.

TSIZE = 2, and one FIFO element = 2 bytes

Maximum TX FIFO level (TX 8 lane) = 2,048/8 = 256 element units

Note: You can set any value below 256 element units for ctl_txhpp_fth; Altera recommends a level of 250 element units or 8'hFA.

The threshold levels on both the transmitter and receiver Atlantic FIFO buffers differ according to implementation. They may depend on the data traffic, the FIFO depth, and the clock frequencies for read and write. Based on your design, you can gauge the usual fill level of the FIFO buffers and determine the appropriate threshold levels.

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