SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

3.1. Atlantic Interface

The Atlantic interface provides a standard mechanism for delivering data to, and accepting data from, the SerialLite II IP core.

It is a full-duplex, synchronous point-to-point connection interface that supports a variety of data widths. The width of the Atlantic interface is determined by the number of lanes and the transfer size.

The SerialLite II IP core allows you to create one or two data ports: one for regular data and one for priority data.
  • Each port has a full Atlantic interface.
  • In the transmit direction of each type of port, an Atlantic dual clock domain FIFO buffer is implemented.
  • The receiver dual clock domain Atlantic FIFO buffer is optional.

The SerialLite II IP core is an Atlantic interface slave when the Atlantic FIFO buffer is implemented (when the function is not in streaming mode, and the buffer size is not zero). Otherwise, the IP core is an Atlantic interface master. The logic that drives data into the SerialLite II IP core or receives data from the SerialLite II IP core is referred as the system logic.

Figure 17. Transmitting and Receiving SerialLite II Data PacketsThis timing diagram shows how the data packets are transmitted and received through the Atlantic interface.


On the transmitter side:
  • The IP core sends the user input data packets to the Atlantic interface when the txrdp_ena signal is asserted (txrdp_ena pin is level triggered).
  • The data packets go through several internal processes in the SerialLite II data link layer and physical layer, including all packet framing, CRC, and 8B/10B generation, and bit serializing.
  • These internal processes produce some core latency of approximately 21 clock cycles to finally send the packets to the High Speed Serial Interface (HSSI) link.
  • The latency calculation is based on the tx_coreclock frequency and is counted from the first data presented at the Atlantic interface on the transmitter side to the first data that appeared at the HSSI.
On the receiver side:
  • The IP core transmits the data packets through the HSSI link and the data packets go through another SerialLite II IP core.
  • In the other SerialLite II IP core, the same reverse processes are done in the SerialLite II data link layer and physical layer to strip off the framing and return the raw data back in the Atlantic interface.
  • The data are presented at the Atlantic interface after approximately 25 clock cycles of latency.
  • The latency is counted from the first data that appeared at the HSSI to the first data that reaches the Atlantic interface on the receiver side.
Note: However, these latencies are based on the simulations and parameters set in the testbench. The latencies vary depending on different designs and implementations, and the fill levels of the Atlantic FIFO buffer in designs where the fill levels are used.
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