SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

4.4.6. Example Testbench – Verilog HDL

Because there is no Atlantic to Atlantic score-boarding, the demonstration testbench focuses on passing error-free data rather than errored data. Any error condition that involves dropped or errored packets, must be handled in the testbench by setting proper expectations

To allow for easy modification of the demonstration testbench, its main section is marked by start–end tags: 

//SERIALLITE2_TB_MAIN_START 
//SERIALLITE2_TB_MAIN_END
Note: This example testbench may not match your testbench exactly.
Table 46.  Example of a Demonstration TestbenchThe table shows and explains a demonstration testbench main section example, allowing you to easily modify the testbench. You can change the packet size, port address, number of packets, and so on, or force certain behavior.
Main Section Comments

//SERIALLITE2_TB_MAIN_START

Start of the testbench main section; the only section intended to be modified.

integer pkt_cnt_dat_dut; integer pkt_cnt_pri_dut; integer pkt_cnt_dat_sis; integer pkt_cnt_pri_sis;

Declare packet counters.

//--------------------------------------------------------- //Define the number of packets / streaming bytes to be sent //--------------------------------------------------------- integer packets_to_send; initial packets_to_send = 5; integer streaming_bytes; initial streaming_bytes = 1500; //---------------------------------------------------------

Defines the number of packets (5) or streaming bytes (1,500) to be sent.

initial begin #1;

Main initial block.

exp_tc_cnt = 1;

Sets expectation for the number of test cases (checks); this number must match the number of tc_start/tc_end pairs in the testbench, otherwise the testbench is declared INCOMPLETE.

err_limit = 0;

Sets expectation for the number of errors.

tc_start(`TBID);

Testcase start.

wait (reset_n == 1);

Waiting for the reset to complete; the reset is asserted in a separate initial block.

// initialize packet counters

 

pkt_cnt_dat_dut = packets_to_send;

Sets the number of packets to be sent to the regular data port of the DUT IP core.

pkt_cnt_pri_dut = packets_to_send;

Sets the number of packets to be sent to the high priority port of the DUT IP core.

pkt_cnt_dat_sis = packets_to_send;

Sets the number of packets to be sent to the regular data port of the SISTER IP core.

pkt_cnt_pri_sis = packets_to_send;

Sets the number of packets to be sent to the high priority port of the SISTER IP core.

wait (linked_up == 1);

Wait for DUT and SISTER to go into link-up.

fork

Launch multiple send packet loops in parallel.

begin ////////////////////////////////////////////// // Generate RDP packets for DUT ////////////////////////////////////////////// @(posedge trefclk);

agen_dat_dut.verbose(1);

agen_dat_dut.ipg(0,5); amon_dat_sis.verbose(1);

fork

while (pkt_cnt_dat_dut > 0) begin : send_loop_dat_dut

integer size;

integer err;

reg [7:0]

addr; addr = $dist_uniform(seed,0,255);

size = $dist_uniform(seed,1,1024);

err = $dist_uniform(seed,0,1);

agen_dat_dut.send_packet(addr,size,err);

reset_watchdog_timer;

pkt_cnt_dat_dut = pkt_cnt_dat_dut - 1;

end

begin

fork amon_dat_sis.wait_all_packets(packets_to_send); join

end

join

end

Send regular data packets (on Atlantic interface) to the DUT.

AGEN and AMON instantiations are set to display verbose messages.

Set AGEN to insert random inner packet gaps.

Launch two processes in parallel:

- Send regular data packets to the DUT.

Define packet size, error, address.

Packet address is a random number from 0 to 255.

Packet size is a random number from 1 to 1,024.

Packet err is a random number from 0 to 1.

Call the AGEN send packet task (regular data, DUT).

Reset watchdog with every packet being sent.

Repeat this loop pkt_cnt_dat_dut times.

- Wait for the other side (Atlantic interface of the SISTER) to receive all these packets.

begin ///////////////////////////////////////////// / // Generate HPP priority packets for SISTER ///////////////////////////////////////////// /

agen_pri_sis.verbose(1);

agen_pri_sis.ipg(0,5);

amon_pri_dut.verbose(1);

fork

while ( pkt_cnt_pri_sis > 0 ) begin : send_loop_pri_sis

integer size;

integer err;

reg [3:0] addr;

addr = $dist_uniform(seed,0,15);

size = $dist_uniform(seed,1,780);

err = ( $dist_uniform(seed,0,8) == 4 ) ? 1'b1 : 1'b0;

agen_pri_sis.send_packet(addr,size,err);

reset_watchdog_timer;

pkt_cnt_pri_sis = pkt_cnt_pri_sis - 1;

end

begin

amon_pri_dut.wait_all_packets(packets_to_send );

end

join

end

Send high priority packets (on Atlantic interface) to the SISTER IP core.

AGEN and AMON instantiations are set to display verbose messages.

Set AGEN to insert random inner packet gaps.

Launch two processes in parallel:

- Send high priority packets to the SISTER.

Define packet size, error, address.

Packet address is a random number from 0 to 15.

Packet size is a random number from 1 to 780.

Packet err is a random number from 0 to 1.

Call the AGEN send packet task (high priority, SISTER).

Reset watchdog with every packet being sent.

Repeat this loop pkt_cnt_pri_sis times.

- Wait for the other side (Atlantic interface of the DUT) to receive all these packets.

join

 

tc_end(`TBID);

exit;

end

All loops must finish (receive all packets) before exiting.

endmodule

End of test case.

Main initial block end.

//SERIALLITE2_TB_MAIN_END

End of testbench main section.
Level Two Title