SerialLite II IP Core User Guide

Download PDF
ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.8.5. Self Synchronized Link Up

The receiver on the far end must synchronize itself to incoming data streams. To do so, it uses the self-synchronizing LSM, a light-weight implementation that is especially useful when data is streaming.

The receiver on the far end must synchronize itself to incoming data streams. To do so, the receiver uses the self-synchronizing LSM, a light-weight implementation that is especially useful when data is streaming. Because there is no handshaking or exchange of status information between the receiver and transmitter, the Self Synchronized Link Up parameter uses considerably fewer logic elements than the full-duplex LSM. The self-synchronizing LSM can be used in all modes, except asymmetric mode, but this mode can only support one lane.

The Self Synchronized Link Up parameter is enabled by default when the IP core operates in unidirectional mode because the duplex LSM cannot be used when there is no return path.

The ctrl_tc_force_train signal must be asserted for the training patterns to be sent. Negate the signal in one of these two conditions:
  • When the adjacent receiver has locked—if this status information can be made available.
  • After a user-defined period of time when the link status of the adjacent receiver is not known or cannot be known.
The LSM links up after receiving 64 consecutive valid, error-free characters. The link goes down after receiving four consecutive errors; at this time, the ctrl_tc_force_train signal should be reasserted until the receiver relocks. The required hold time for the ctrl_tc_force_train signal largely depends on when the ALTGX or Custom PHY IP core completes the power-on reset cycle. The self-synchronizing link-up state machine does not look at the incoming stream until the transceiver reset is complete.
Note: The Arria II GX and Stratix IV devices use the ALTGX IP core. The later devices use the Custom PHY IP core.
For example, the following procedure shows the transceiver reset sequence in a transceiver device:
  1. Wait for the pll_locked signal (stat_tc_pll_locked) to be asserted, which happens when the PLL in the ALTGX or Custom PHY IP core locks to the reference clock (trefclk). The reference clock must be characterized—10 ms or less is normal.
  2. Wait for the rx_freqlocked signal (stat_rr_freqlock) to be asserted, which happens when the ALTGX or Custom PHY IP core locks onto the serial stream—5 ms or less is normal.
  3. The Rx digital reset needs to complete; this reset normally takes one million internal tx_coreclock cycles after rx_freqlocked is asserted. The stat_tc_rst_done signal is asserted to indicate that the reset sequence has been completed.
Note: The normal time values are much shorter in simulation, (for example, IP Functional Simulation Model), but not in gate-level simulation. Gate-level simulation uses the hardware equivalent time values.

You should characterize the timing of the signals in the transceiver reset sequence to set up the size of your ctrl_tc_force_train counter. The IP core also has a reset done status signal (stat_tc_rst_done) that can be useful for measurements.

The following SerialLite II status output signals correspond to each step above:
  • stat_tc_pll_locked
  • stat_rr_freqlock
  • stat_tc_rst_done (to see when rx_digitalreset has been negated)
After the reset controller completes, the IP core waits for the transceiver byte aligner to detect and align the control (k28.5) character in the training sequence. When the transceiver detects this character, the count starts at every k28.5 that is received (basically, counting every training sequence). Once 64 error-free training sequences have been received, the IP core reports linkup. Any errors (for example, disparity or 8B/10B errors) that are received reset the count, and the IP core continues to wait until 64 error-free training patterns are received.
Note: The self-synchronizing LSM also locks onto the clock compensation sequence.

For Arria II GX and Stratix IV devices, you can turn on the Enable frequency offset tolerance option to allow the receiver to automatically relock if the link goes down. Therefore, the transmitter is not required to assert ctrl_tc_force_train to retrain the link (which may be impossible in a unidirectional link because the transmitter does not necessarily detect that the receiver has lost the link).

For Arria V, Cyclone V, and Stratix V devices, you have to expose and integrate all the related signals from the transceiver.

Level Two Title