SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

3.6. SerialLite II Signals

The signals required for a given configuration, as well as the appropriate bus widths, are created automatically by the SerialLite II parameter editor based upon the parameter values you select.
Table 24.  High-Speed Serial Interface Signals
Signal Direction Clock Domain Description
rxin [n-1]

n = RX number of lanes

Output – SerialLite II differential receive data bus.
Bus carries packets, cells, or in-band control words.
Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
txout[m-1]

m = TX Number of lanes

Output – SerialLite II differential transmit data bus.
Bus carries packets, cells, or in-band control words.
Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
rrefclk Output rrefclk Receive core output PLL-derived clock.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed. For example, rrefclk0 is the signal from SerialLite II receiver block 0.
trefclk Input trefclk Reference clock used to drive the transmitter PLL.
The PLL is used to generate the transmit core clock (tx_coreclock).
Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
tx_coreclock Output tx_coreclock Transmitter core output clock. In Arria® II GX and Stratix® IV designs, the TX PLL output clock and the primary clock are used for the TX logic.
mreset_n Input Asynchronous Master reset pin, active low. Asserting this signal causes the entire SerialLite II IP core, including the Atlantic FIFO buffers, to be reset.

For Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V designs, hold this signal asserted until the Custom PHY asserts the tx_ready and rx_ready output ports.

ctrl_tc_force_train Input tx_coreclock Force training patterns to be sent. Negate once the receiver has locked. Only used in self-synchronizing mode. Otherwise, this signal is currently reserved (tie this signal to 1'b0).
stat_tc_pll_locked Output tx_coreclock PLL locked signal. Indicates that the ALTGX PLL has locked to trefclk.
stat_rr_link Output rrefclk Link Status. When high, the link is enabled.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed. For example, stat_rr_link0 is the signal from SerialLite II receiver block 0.

Table 25.  Transceiver Signals rxnl is the receive number of lanes;

txnl is the transmit number of lanes;

srx is the transfer size × the receive number of lanes.

Signal Direction Clock Domain Description
ctrl_tc_serial_lpbena Input tx_coreclock Serial Loopback (TXOUT internally connected to RXIN).

Tie signal to 1'b0 to not use loopback and tie to 1'b1 to use serial loopback.

rcvd_clk_out [rxnl-1:0] Output – Per lane recovered clock.
Note: Not applicable for Arria® V, Cyclone® V, and Stratix® V devices.
err_rr_8berrdet [srx-1:0] Output/ Input rrefclk 8B/10B error detection signal.
Note: Output port for Arria® II GX and Stratix® IV devices; input port for Arria® V, Cyclone® V, and Stratix® V devices.
err_rr_disp [srx-1:0] Output/ Input rrefclk Disparity error detection signal.
Note: Output port for Arria® II GX and Stratix® IV devices; input port for Arria® V, Cyclone® V, and Stratix® V devices.
err_rr_pcfifo_uflw [rxnl-1:0] Output rrefclk Interface/phase compensation FIFO buffer underflow signal ( Arria® II GX and Stratix® IV devices only).
err_rr_pcfifo_oflw [rxnl-1:0] Output rrefclk Interface/phase compensation FIFO buffer overflow signal. ( Arria® II GX and Stratix® IV devices only)
err_rr_rlv] [rxnl-1:0] Output rrefclk Run length violation status signal. ( Arria® II GX and Stratix® IV devices only)
err_tc_pcfifo_uflw [txnl-1:0] Output tx_coreclock Interface/phase compensation FIFO buffer underflow signal.
Note: This signal is removed in configurations targeted for Arria® V and Stratix® V devices due to the exclusion of hard transceivers.
err_tc_pcfifo_oflw [txnl-1:0] Output tx_coreclock Interface/phase compensation FIFO buffer overflow signal.
( Arria® II GX and Stratix® IV devices only)
Note: This signal is removed in configurations targeted for Arria® V and Stratix® V devices due to the exclusion of hard transceivers.
stat_rr_gxsync[srx-1:0] Output rrefclk Gives the status of the pattern detector and word aligner.
Note: This signal is removed in configurations targeted for Arria® V and Stratix® V devices due to the exclusion of hard transceivers. If needed, you can use the rx_syncstatus signal generated when you create optional word aligner status port during the Custom PHY generation.
stat_rr_rxlocked [rxnl-1:0] Output rrefclk Receiver PLL locked signal. Indicates whether or not the receiver PLL is phase locked to the CRU reference clock. When the PLL locks to data, which happens some time after the transceiver’s rx_freqlocked signal is asserted high, this signal has little meaning because it only indicates lock to the reference clock. This signal is active high for Arria® II GX and Stratix® IV devices.
Note: This signal is removed in configurations targeted for Arria® V and Stratix® V devices due to the exclusion of hard transceivers. If needed, you can use the rx_is_lockedtoref signal generated when you create additional ports during the Custom PHY instantiation.
stat_rr_freqlock [rxnl-1:0] Output rrefclk Frequency locked signal from the CRU. Indicates whether the transceiver block receiver channel is locked to the data mode in the rxin port.
Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers. If needed, you can use the rx_is_lockedtodata signal generated when you create additional ports during the Custom PHY instantiation.
stat_rr_pattdet [srx-1:0] Output/ Input rrefclk Pattern detection signal
Note: Output port for Arria® II GX and Stratix® IV devices; input port for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices.
reconfig_fromgxb ]

Arria® II GX/ Stratix® IV GX: [recon_quad*17-1:0]

Output reconfig_clk ALTGX Reconfig from the GXB Bus. This signal is connected to the reconfig_fromgxb port on the altgx_reconfig module.
If you use Arria® II GX or Stratix® IV device, you must connect this output to the altgx_reconfig module for offset cancellation.
Note: recon_quad is the total number of Quads being used.

If the altgx_reconfig block is not used, the signal will not toggle (set to a fixed value) and thus is not on any clock domain. If the altgx_reconfig block is used, this signal is on the reconfig_clk domain.

Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
reconfig_togxb

Arria® II GX/ Stratix® IV GX: [3:0]

Input reconfig_clk ALTGX Reconfig to the GXB Bus. This signal is connected to the reconfig_togxb port on the altgx_reconfig module.

If you use Arria® II GX or Stratix® IV device, you must connect this output to the altgx_reconfig module for offset cancellation.

Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
reconfig_clk Input – ALTGX Reconfig Clock to the GXB. This signal is connected to the reconfig_clk port on the altgx_reconfig module.

If you use Arria® II GX or Stratix® IV device, you must connect this output to the altgx_reconfig module for offset cancellation.

Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
cal_blk_clk Input – Calibration clock for the termination resistor calibration block. The frequency range of cal_blk_clk is 10 to 125 MHz.
Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.
gxb_powerdown Input –

Transceiver block reset and power down. This signal resets and powers down all circuits in the transceiver block. This does not affect the refclk buffers and reference clock lines.

All the gxb_powerdown input signals of cores placed in the same transceiver block should be tied together. The gxb_powerdown signal should be tied low or should remain asserted for at least 2 ms whenever it is asserted.

Note: This signal is removed in configurations targeted for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices due to the exclusion of hard transceivers.

Table 26.  Atlantic Interface SignalsThese signals are only present when the Link Layer mode is enabled and the Atlantic FIFO buffer is used.
Note: There are no specific requirements for Atlantic clocks (rxrdp_clk, rxhpp_clk, txrdp_clk, and txhpp_clk) as they are all system dependent. The Atlantic clocks at the read side must be fast enough to prevent backpressure which decreases bandwidth efficiency.
Signal Direction Clock Domain Description
rxrdp_clk Input – Atlantic receive regular data port clock.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
txrdp_clk Input – Atlantic transmit regular data port clock.
rxhpp_clk Input – Atlantic receive high priority port clock.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
txhpp_clk Input – Atlantic transmit high priority port clock.
rxrdp_ena Input rxrdp_clk Enable signal on the Atlantic interface. Indicates that the data is to be read on the next clock cycle.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_dav Input rxrdp_clk Input (No FIFO buffer) determines whether flow control is required on this port. When this signal is low, the fill level has been breached. When this signal is high, the FIFO buffer has enough space for more words.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_dav Output rxrdp_clk Output (With FIFO buffer) represents the buffer’s fill level. This signal is high when the level is above FTL or if an EOP is in the buffer.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_val Output rxrdp_clk The output data is valid.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_sop Output rxrdp_clk Start of packet indicator on the Atlantic interface.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_eop Output rxrdp_clk End of packet indicator on the Atlantic interface.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_err Output rxrdp_clk Error indicator on the Atlantic Interface. This signal is not necessarily held high until rxrdp_eop is asserted.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_mty[m-1:0] Output rxrdp_clk Number of empty bytes in the data word.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
Note: d is the empty value, which is log2 (data width).
rxrdp_dat[d-1:0] Output rxrdp_clk User data bits.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
Note: m is the data width, which is 8 × transfer size × the RX number of lanes.
rxrdp_adr[7:0] Output rxrdp_clk User-defined packet ID. Only valid with rxrdp_sop.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
txrdp_ena Input txrdp_clk Enable signal on the Atlantic interface. Indicates that the data is valid.
txrdp_dav Output txrdp_clk Indicates that the input FIFO buffer is not full.
txrdp_sop Input txrdp_clk Start of packet indicator on the Atlantic interface.
txrdp_eop Input txrdp_clk End of packet indicator on the Atlantic interface.
txrdp_err Input txrdp_clk Error indicator on the Atlantic interface.
txrdp_mty[tm-1:0] Input txrdp_clk Number of empty bytes in the data word.
Note: tm is the empty value, which is log2 (data width).
txrdp_dat[td-1:0] Input txrdp_clk User data bits.
Note: td is the data width, which is 8 × transfer size × the TX number of lanes.
txrdp_adr[7:0] Input txrdp_clk User-defined packet ID.
rxhpp_ena Input rxhpp_clk Enable signal on the Atlantic interface. Indicates that the data is to be read on the next clock cycle.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_dav Input rxhpp_clk Input (No FIFO buffer) determines whether flow control is required on this port. When this signal is low, the fill level has been breached. When this signal is high, the FIFO buffer has enough space for more words.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_dav Output rxhpp_clk Output (With FIFO buffer) represents the buffer’s fill level. This signal is high when the level is above FTL or if an EOP is in the buffer.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_val Output rxhpp_clk The output data is valid.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_sop Output rxhpp_clk Start of packet indicator on the Atlantic interface.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_eop Output rxhpp_clk End of packet indicator on the Atlantic interface.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_err Output rxhpp_clk Error indicator on the Atlantic Interface. This signal is not necessarily held high until rxhpp_eop is asserted.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxhpp_mty [m-1:0] Output rxhpp_clk Number of empty bytes in the data word.
Note: In broadcast mode, these signals will have the corresponding receiver function number post-fixed.
Note: m is the empty value, which is log2 (data width).
rxhpp_dat [d-1:0] Output rxhpp_clk User data bits.
Note: In broadcast mode, these signals will have the corresponding receiver function number post-fixed.
Note: d is the data width, which is 8 × transfer size × the RX number of lanes.
rxhpp_adr[3:0] Output rxhpp_clk User-defined packet ID. Only valid with rxhpp_sop.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
txhpp_ena Input txhpp_clk Enable signal on the Atlantic interface. Indicates that the data is valid.
txhpp_dav Output txhpp_clk Indicates that the input FIFO buffer is not full.
txhpp_sop Input txhpp_clk Start of packet indicator on the Atlantic interface.
txhpp_eop Input txhpp_clk End of packet indicator on the Atlantic interface.
txhpp_err Input txhpp_clk Error indicator on the Atlantic interface.
txhpp_mty [tm-1:0] Input txhpp_clk Number of empty bytes in the data word.
Note: tm is the empty value, which is log2 (data width).
txhpp_dat [td-1:0] Input txhpp_clk User data bits.
Note: td is the data width, which is 8 × transfer size × the TX number of lanes.
txhpp_adr[3:0] Input txhpp_clk User-defined packet ID.

Table 27.  Atlantic Interface Signals for Streaming Mode
Signal Direction Clock Domain Description
rxrdp_dat [d-1:0] Output rrefclk Received user data bits.
Note: d is = FIFO SIZE / (TSIZE * RX Number of lanes).
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
rxrdp_ena Output rrefclk Enable signal on the Atlantic interface.
Indicates that the data is valid on the current clock cycle.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
txrdp_dat [td-1:0] Input tx_coreclock User data bits to be transmitted.
Note: td is = FIFO SIZE / (TSIZE * TX Number of lanes).
txrdp_ena Input tx_coreclock Enable signal on the Atlantic interface.

Indicates that the data is valid.

txrdp_dav Output tx_coreclock Indicates that the core is requesting the user data to stop while the core inserts the clock compensation sequence.

If Enable frequency offset tolerance is not turned on, this signal will always be high when the link is up.

Table 28.  Protocol Processor’s Error, Status and Control Signals
Signal Direction Clock Domain Description
err_rr_rxrdp_oflw Output rrefclk Indicates that the Atlantic FIFO buffer has overflowed and data has been lost when Enable frequency offset tolerance is turned off (regular data port).
err_rr_rxhpp_oflw Output rrefclk Indicates that the Atlantic FIFO buffer has overflowed and data has been lost when Enable frequency offset tolerance is turned off (priority data port).
err_tc_rxrdp_oflw Input tx_coreclock Indicates that the Atlantic FIFO buffer has overflowed and data has been lost when Enable frequency offset tolerance is turned on (regular data port).
err_tc_rxhpp_oflw Input tx_coreclock Indicates that the Atlantic FIFO buffer has overflowed and data has been lost when Enable frequency offset tolerance is turned on (priority data port).
err_txrdp_oflw Output txrdp_clk Indicates that the Atlantic FIFO buffer has overflowed and data has been lost (regular data port).
err_txhpp_oflw   txhpp_clk Indicates that the high-priority Atlantic FIFO buffer has overflowed and data has been lost. If the Retry-on-error parameter is turned on, this signal remains high until the FIFO buffer has been emptied by the SerialLite II IP core.
stat_rxrdp_empty   rxdrp_clk Indicates that the internal Atlantic FIFO buffer is empty, and the read request is ignored.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_rxhpp_empty   rxhpp_clk Indicates that the internal Atlantic FIFO buffer is empty, and the read request is ignored.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
ctl_rxhpp_ftl [n-1:0])   rxhpp_clk Receive high priority port FIFO threshold low (dav control). Determines when to inform the user logic that data is available via the rxhpp_dav signal. This threshold applies to all buffers. Units are in elements. Only change at reset.
Note: n is = FIFO SIZE / (TSIZE * RX Number of lanes).
ctl_rxrdp_ftl [n-1:0]   rxrdp_clk Receive regular data port FIFO threshold low (dav control). Determines when to inform the user logic that space is available via the rxrdp_dav signal. This threshold applies to all buffers. Units are in elements. Only change at reset.
Note: n is = FIFO SIZE / (TSIZE * RX Number of lanes).
ctl_rxhpp_eopdav   rxhpp_clk Receive high priority port FIFO buffer end-of-packet (EOP)-based dav control. Assert to turn on dav when there is an end of packet below the FTL threshold. Value applies to all Atlantic buffers. Only change at reset.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
ctl_rxrdp_eopdav   rxrdp_clk Receive regular data port FIFO buffer EOP-based dav control. Assert to turn on dav when there is an end of packet below the FTL threshold. Value applies to all Atlantic buffers. Only change at reset.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
ctl_txhpp_fth [tn-1:0]   txhpp_clk Transmit high priority port FIFO buffer threshold high dav control.
Note: tn is = FIFO SIZE / (TSIZE * TX Number of lanes).
ctl_txrdp_fth [tn-1:0]   txrdp_clk Transmit regular data port FIFO buffer threshold high dav control.
Note: tn is = FIFO SIZE / (TSIZE * TX Number of lanes).

Table 29.  Troubleshooting SignalsThese signals do not necessarily need to be connected to external logic. In general, they are for diagnostic purposes. Some signals are only available in certain configurations.
Signal Direction Clock Domain Description
stat_tc_rst_done Output tx_coreclock Reset controller logic Done signal. When high, the reset controller has completed the ALTGXB reset sequence successfully.
Note: Not applicable for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices because the transceiver is generated independently. For these devices, you can find out if the transceiver is ready by polling on the tx_ready or rx_ready signals from the Custom PHY IP core.
err_rr_foffre_oflw Output rrefclk Indicates that frequency offset tolerance FIFO buffer has overflowed. The link restarts.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_tc_foffre_empty Output tx_coreclock Indicates that frequency offset tolerance FIFO buffer has underflowed. The link does not go down. IDLE characters are inserted. This does not have a negative impact on the core, and is simply for diagnostic purposes.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_rr_ebprx Output rrefclk Indicates that an end of bad packet character was received.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_bip8 Output rrefclk Indicates that a BIP-8 error was detected in the received link management packet.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_crc Output rrefclk Indicates that a CRC error was detected in the received segment/packet.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_fcrx_bne Output rrefclk Indicates that a flow control link management packet was received, but flow control is not enabled.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_roerx_bne Output rrefclk Indicates that a retry-on-error link management packet was received, but Retry-on-error parameter is not enabled.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_invalid_lmprx Output rrefclk Indicates that an invalid link management packet was received.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_missing_start_dcw Output rrefclk Indicates that data byte(s) received, but a start of data control word (DCW) is missing.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_addr_mismatch Output rrefclk Indicates that the start and end address fields do not match. Segments are marked with an error. Possible packets are destined for an invalid address.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_pol_rev_required Output rrefclk May indicate catastrophic error. Polarity on the input ALTGXB lines is reversed; the IP core cannot operate. If you see the signal for the first time, you should manually reset the core. If the signal triggers again after you reset, then it confirms a catastrophic error.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_rr_dskfifo_oflw Output rrefclk Indicates that deskew FIFO buffer has overflowed. Link restarts.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_rr_dskw_done_bc Output rrefclk Indicates that a bad column was received after successful deskew completion. Link is restarted.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_tc_rdp_thresh_breach Output rrefclk Indicates that the receiver regular data port FIFO buffer is breached, transmit flow control link management packet.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
stat_tc_hpp_thresh_breach Output tx_coreclock Indicates that the receiver priority data port FIFO buffer is breached, transmit flow control link management packet.
Note: In broadcast mode, this signal will have the corresponding receiver function number post-fixed.
err_tc_roe_rsnd_gt4 Output tx_coreclock Indicates that the transmitter has transmitted a segment four times without receiving an ACK for that segment. The link is restarted.
stat_tc_roe_timeout Output tx_coreclock Retry-on-error only: Indicates that the transmitter has timed out waiting for ACK for a packet. The IP core sends that packet again.
stat_tc_fc_rdp_retransmit Output tx_coreclock Indicates that the receiver FIFO buffer is still breached, and the refresh timer has reached maximum. Retransmitting flow control link management packet (regular data port).
stat_tc_fc_hpp_retransmit Output tx_coreclock Indicates that the receiver FIFO buffer is still breached, and the refresh timer has reached maximum. Retransmitting flow control link management packet (priority data port).
err_tc_is_drop Output tx_coreclock Indicates that irregular segment received (segment size boundary violation).
err_tc_lm_fifo_oflw Output tx_coreclock Indicates that the link management FIFO buffer has overflowed. Link management packets are lost.
err_rr_rx2txfifo_oflw Output rrefclk Indicates that the receiver to transmitter link management status information FIFO buffer has overflowed.
stat_rr_fc_rdp_valid Output rrefclk Indicates that a flow control link management packet was received (regular data port).
stat_rr_fc_hpp_valid Output rrefclk Indicates that a flow control link management packet was received (priority data port).
stat_rr_fc_value[7:0] Output rrefclk Indicates that the RAW FC_TIME value is embedded in the valid flow control link management packet. Decode with the stat_rr_fc_rdp_valid and stat_rr_fc_hpp_valid signals.
stat_rr_roe_ack Output rrefclk Indicates that a retry-on-error link management packet of type ACK was received.
stat_rr_roe_nack Output rrefclk Indicates that a retry-on-error link management packet of type NACK was received.
Level Two Title