SerialLite II IP Core User Guide

Download PDF
ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

6. Document Revision History for the SerialLite II IP Core User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.07.13 16.1 16.1
  • Removed support for Intel® Stratix® 10 devices.
  • Rebranded as Intel.

Date

Version

Changes

January 2019 2019.01.09 Added note in the Reference Clock Frequency topic to clarify that supported reference clock frequency is dependent on device. Users should refer to each device datasheet for the supported reference clock frequency range.
October 2016 2016.10.28
  • Added indirect support for Intel® Stratix® 10 devices. Contact an Altera representative or file a Service Request (SR) to use the Intel® Stratix® 10 devices.
May 2016 2016.05.02
  • Edited aggregate bandwidth information—the input data bus into the processor portion is 36 bits wide (32 bits of raw data and 8 bits of control information).
  • Added indirect support for Arria 10 devices. Contact an Altera representative or file a Service Request (SR) to use the Arria 10 devices.
  • Updated transceiver information for Arria 10, Arria V, Cyclone V, and Stratix V devices. You need to generate the Custom PHY IP core for these devices.
  • Changed instances of Quartus II to Quartus Prime.
  • Added links to archived versions of the SerialLite II IP Core User Guide.
July 2014 2014.07.09
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed obsolete device information.
January 2014 13.1
  • Removed information about Arria GX, HardCopy IV, Stratix GX, and Stratix II GX devices. Altera no longer supports these devices.
  • Added Cyclone V device support.
  • Updated data rate information.
July 2012 12.0
  • Added Arria V and Stratix V device support.
  • Added information about MegaCore configuration for Arria V and Stratix V devices.
February 2011 10.1
  • Updated Arria II GX and Stratix IV device support information.
  • Added information about FIFO threshold settings.
July 2010 10.0

Updated Stratix IV device support information.
November 2009 9.1
  • Added HardCopy IV GX device support.
  • Added timing diagrams in Initialization and Restart, and Atlantic Interface sections.

March 2009

9.0

Added Arria II GX device support.

November 2008

8.1

Added requirement to configure a dynamic reconfiguration block with Stratix IV transceivers, to enable offset equalization.

May 2008

8.0

  • Added additional ALT2GXB parameters - VCCH, Reference Input Clk Frequency, and Reconfiguration Channel Number.
  • Added Stratix IV device support.

October 2007

7.2

(Beta)

  • Added gxb_powerdown signal to ease merging of multiple SerialLite II cores into the same transceiver block.
  • Added VHDL testbench for some configurations.
  • Moved the ALT2GXB megafunction instantiation into a separate file to ease post-generation changes.
Level Two Title