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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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6.2.2.1. Specifying Target FPGA and Clock Settings
To specify target FPGA and clock settings in Qsys, perform the following steps:
- Click Device Family in View menu, select the Device Family that matches the Arria® 10 device you are targeting. Warning will appear if the selected device family does not match Quartus® Prime project settings, you need to make sure your selected device in Quartus® Prime project settings match to your selected Device Family in Qsys.
- On the System Contents tab, double click the clk_0 component. In the Parameters tab for clk_0, set the Clock frequency to 50MHz.
Next, you begin to add other IP cores to the Qsys system.