Visible to Intel only — GUID: sss1453958203318
Ixiasoft
1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
Visible to Intel only — GUID: sss1453958203318
Ixiasoft
6.3.3. Launching Signal Tap Logic Analyzer
To observe the signals monitored by the Signal Tap, you must launch the Signal Tap Logic Analyzer and start the Signal Tap operation before the fault injection operation. To launch the Signal Tap Logic Analyzer, perform the following steps:
- Launch Signal Tap Logic Analyzer from Tools menu.
- Make sure the Hardware and Device is selected.
Your Signal Tap operation cannot be started at this point until the FPGA is configured.