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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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Ixiasoft
6.2.4. Integrating Qsys System into Quartus Prime Project
To complete the reference design, you must perform the following tasks:
- Generate In-System Source and Probe (ISSP) IP core
- Quartus® Prime project setting and add the following files (provided in download package) to the project:
- Top.v—instantiate the Qsys system module and connect all other IP cores
- Top.stp—monitor some key signals with Signal Tap tool
- Top.sdc—timing constraint
- Assign ASD regions to up counter and down counter
- Assign FPGA device and pin locations
- Compile the project