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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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6.2. Creating Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys
The a10-seu.zip reference design consists of:
- a10_seu.qar—the project archive file
- top.v—the top level module of the project
- top.sdc—the timing constraint file
- top.stp—the Signal Tap file
Note: The a10-seu-complete.zip consists of a fully compiled and output files-ready reference design. You can refer directly to Design Testing with Fault Injection Debugger if you choose to use this complete design as a reference.
In this design, you will use Platform Designer (Standard) to connect the Intel SEU-related IP cores together. IP core to be connected are EMR Unloader IP core, Fault Injection IP core and Advanced SEU Detection IP core. Some other IP cores are also needed to make the design complete, which are Altera IOPLL IP core, AVST Splitter and Serial Flash Controller IP core.
Figure 11. Arria 10 SEU Fault Injection and Hierarchy Tagging Design