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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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7. Implementing ECC Feature in Arria® 10 ROM Design
The ROM IP core does not have ECC selection in the user interface. However, you can enable the ECC feature for ROM design by using the RAM: 2-PORT IP core.
Steps to implement the ECC feature in Arria® 10 ROM Design.
- Instantiate the RAM: 2-PORT IP with the following settings:
Parameters | Settings |
---|---|
Operation Mode | Select With one read port and one write port. |
Use different data width on different ports | Disable |
RAM Block Type | Select M20K. |
Create byte enable for port A and Create byte enable for port A | Disable |
Enable Error Correction Checking | Enable |
Do you want to specify the initial content of the memory? | Select Yes, use this file for the memory content data and specify the location of the file. |
- Connect the signals of the IP according to the following figure.
Figure 13. ROM with ECC Feature Using RAM: 2-PORT IP