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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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4.1.2.2. Reading EMR using HPS
The FPGA Manager in the HPS has the ability to monitor the CRC_ERROR status pin and to retrieve the error symptom, location and type. You can choose to enable the CRC error interrupt from the FPGA Manager, followed by CRC error information extraction from respective registers.
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