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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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6.2.2.7. Adding Serial Flash Controller
You must use the Serial Flash Controller IP core to access to the EPCQ-L1024 that stores the SMH file in this reference design. The ASD IP core reads the SMH data from EPCQ-L1024 via Serial Flash Controller IP core. To add the Serial Flash Controller, perform the following steps:
- On the IP Catalog tab, expand Basic Functions, expand Configuration and Programming, and then click Altera Serial Flash Controller.
- Click Add. The Altera Serial Flash Controller parameter editor appears. Set the parameters as the follows:
- On Configuration device type list, select EPCQL1024.
- On Choose I/O mode, select QUAD.
- On Number of Chip Selects used list, select 1.
- Click Finish to return to Qsys. On the System Content tab, an instance of the epcq_controller_0 appears in the system contents table.
- Connect outclk1 port of iopll_0 to clock_sink port of epcq_controller_0.
Note: The Fmax for Serial Flash Controller is 25MHz
- Connect clk_reset port of clk_0 clock source to reset port of epcq_controller_0.
- Connect asd_sp_master port of adv_seu_detection_0 to avl_mem port of epcq_controller_0.