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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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Ixiasoft
6.2.2.2. Adding Altera IOPLL IP Core
You must instantiate Altera IOPLL IP core in this reference design to generate 3 different clock sources, 10MHz, 20MHz and 100MHz. To add the Altera IOPLL IP core, perform the following steps:
- On the IP Catalog Tab, expand Basic Functions, expand Clock; PLLs and Resets, PLL, and then click Altera IOPLL.
- Click Add. The Altera IOPLL parameter editor appears.
- On PLL tab, at General section, set the Reference Clock Frequency to 50.
- Uncheck Enable locked output port.
- At Output Clocks section, set Number Of Clocks to 3.
- Set the clocks as the following:
- For outclk0, set the Clock Name to clk_100and set the Desired Frequency to 100MHz.
- For outclk1, set the Clock Name to clk_20 and set the Desired Frequency to 20MHz.
- For outclk2, set the Clock Name to clk_10 and set the Desired Frequency to 10MHz.
- Click Finish to return to Qsys.
- On System Contents tab, an instance of the iopll_0 appears in the system contents table.
- Connect the clk port of the clk_0 clock source to the refclk port of the iopll_0.
- Connect the clk_reset port of the clk_0 clock source to the reset port of the iopll_0.
- Double click the outclk2 of the iopll_0 at Export column to export outclk2 as the clock source for other component outside of this Qsys system. Rename the exported signal as clk_10.
- Double click the outclk0 of the iopll_0 at Export column to export outclk0 as the clock source for other component outside of this Qsys system. Rename the exported signal as clk_100.