AN 737: SEU Detection and Recovery in Arria® 10 Devices

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ID 683064
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quartus® Prime Software SEU FIT Reports 3. Arria® 10 Error Detection and Correction Feature Architecture 4. Guidelines for Error Detection CRC and Error Correction Feature 5. Guidelines for Embedded Memory ECC Feature 6. Arria® 10 EDCRC Reference Design 7. Implementing ECC Feature in Arria® 10 ROM Design 8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
2. Quartus® Prime Software SEU FIT Reports x
2.1. Enabling the Projected SEU FIT by Component Usage Report 2.2. SEU FIT Parameters Report 2.3. Projected SEU FIT by Component Usage Report
2.3. Projected SEU FIT by Component Usage Report x
2.3.1. Component FIT Rates 2.3.2. Raw FIT 2.3.3. Utilized FIT 2.3.4. Mitigated FIT 2.3.5. Architectural Vulnerability Factor
2.3.3. Utilized FIT x
2.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 2.3.3.2. Considerations for Small Designs
3. Arria® 10 Error Detection and Correction Feature Architecture x
3.1. Error Detection and Correction for CRAM 3.2. Memory Blocks Error Correction Code Support
3.1. Error Detection and Correction for CRAM x
3.1.1. Error Detection Cyclic Redundancy Check 3.1.2. Recovering from CRC Errors
3.1.1. Error Detection Cyclic Redundancy Check x
3.1.1.1. Column-Based and Frame-Based Check-Bits 3.1.1.2. Error Message Register
4. Guidelines for Error Detection CRC and Error Correction Feature x
4.1. Error Detection 4.2. Enabling Error Correction (Internal Scrubbing) 4.3. Interpreting CRC_ERROR
4.1. Error Detection x
4.1.1. Enabling Error Detection 4.1.2. Reading EMR
4.1.1. Enabling Error Detection x
4.1.1.1. Enabling the Error Detection CRC_ERROR Pin
4.1.2. Reading EMR x
4.1.2.1. Reading EMR using EMR Unloader IP Core 4.1.2.2. Reading EMR using HPS 4.1.2.3. Reading EMR using JTAG Interface
4.3. Interpreting CRC_ERROR x
4.3.1. CRC_ERROR Pin Behavior 4.3.2. Correctable and Uncorrectable Error
6. Arria® 10 EDCRC Reference Design x
6.1. System Requirements 6.2. Creating Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys 6.3. Design Testing with Fault Injection Debugger
6.2. Creating Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys x
6.2.1. Starting Quartus® Prime Software and Opening the Reference Design Project 6.2.2. Creating New Qsys System 6.2.3. Generating Qsys System 6.2.4. Integrating Qsys System into Quartus Prime Project
6.2.2. Creating New Qsys System x
6.2.2.1. Specifying Target FPGA and Clock Settings 6.2.2.2. Adding Altera IOPLL IP Core 6.2.2.3. Adding EMR Unloader IP Core 6.2.2.4. Adding Advance SEU Detection IP Core 6.2.2.5. Adding Fault Injection IP Core 6.2.2.6. Adding Avalon-ST Splitter 6.2.2.7. Adding Serial Flash Controller
6.2.4. Integrating Qsys System into Quartus Prime Project x
6.2.4.1. Generating In-System Source and Probe IP Core 6.2.4.2. Quartus Prime Project Settings 6.2.4.3. Assigning ASD Regions 6.2.4.4. Assigning FPGA Pin Location 6.2.4.5. Compiling the Project
6.3. Design Testing with Fault Injection Debugger x
6.3.1. Converting .sof File and .smh File to .jic File 6.3.2. Programing .jic File into EPCQ-L 6.3.3. Launching Signal Tap Logic Analyzer 6.3.4. Configuring Arria® 10 and Reading .smh File with Fault Injection Debugger 6.3.5. Injecting Error with Fault Injection Debugger
7. Implementing ECC Feature in Arria® 10 ROM Design x
7.1. Examples of Error Detection and Correction
1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices

4.3.1. CRC_ERROR Pin Behavior

The Arria® 10 fast EDCRC feature runs all the column-based check-bits engine in parallel. When an SEU is detected, the column-based check-bits asserts the CRC_ERROR, the detected frame location is then passed to the frame-based check-bits to further localize the affected bit. This process causes the CRC_ERROR pin to assert twice. Column-based check-bits assert the first CRC_ERROR pulse and followed by the frame-based check-bits asserting the second pulse.

In Arria® 10, as soon as an SEU is detected, the CRC_ERROR is asserted high and remains high until the EMR is ready to be read. You can unload the EMR data as soon as the CRC_ERROR pin goes low. Once EMR data is unloaded, can determine the error type and the affected location. With these information you can decide how your system should respond to the specific SEU event.

Figure 7. Fast EDCRC Process Flow Chart
Figure 8. Timing Diagram for Column-Based Check-BitsIf the error is correctable, in most cases, there is a second pulse in a single SEU event .There are cases where the error is uncorrectable when the CRC_ERROR pin asserts 2 pulses, refer to Correctable and Uncorrectable Error for complete correctable and uncorrectable error cases. The complete EMR is only available at the falling edge of the second pulse.

In the rare event of an uncorrectable and un-locatable error, the CRC_ERROR signal is asserted only once. There is no second pulse assertion by frame-based check-bits due to the uncorrectable error location cannot be located. The statistical likelihood of uncorrectable multi-bit SEU is less than one in 10,000 years for a device in typical environmental conditions.

Figure 9. Timing Diagram for Column-Based or Frame-Based Check-BitsExample of CRC_ERROR pin behavior for column-based/frame-based check-bits with a single pulse observed in one SEU event.
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