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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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4.1.1.1. Enabling the Error Detection CRC_ERROR Pin
To enable the CRC_ERROR pin for external host monitoring purpose, perform the following steps:
- On the Assignments menu, click Device.
- Click Device and Pin Options and select the Error Detection CRC at the left panel.
- Check the Enable Error Detection CRC_ERROR pin.
- Select the EDCRC clock divisor from the list of Divide error check frequency by.
Note: This option provides you with a flexibility to run the EDCRC at a slower speed. However, Intel recommends you to set to the smallest EDCRC clock divisor. Setting a high divisor can impact the error detection time performance. Refer to Arria 10 Handbook SEU Mitigation chapter of the Arria 10 handbook for detection time specification.
- Check the Enable open drain on CRC_ERROR pin if you have an external pull up resistor on your board.
- Click OK.
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