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1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
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6. Arria® 10 EDCRC Reference Design
The EDCRC reference design demonstrates the following main SEU detection and recovery for Arria® 10:
- Instantiating various SEU-related IP cores such as EMR Unloader IP core, Advanced SEU Detection IP core, and Fault Injection IP core
- Demonstrating how the Advanced SEU Detection IP core retrieves the SMH information from the EPCQ-L with Serial Flash Controller IP core2
- Integrating the reference design into your system and characterize your system response to the SEU event with the Intel Fault Injection feature.
Section Content
System Requirements
Creating Arria 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys
Design Testing with Fault Injection Debugger
2 You can only use EPCQ-L to store SMH and access with Serial Flash Controller when you set your MSEL pin to Active Serial Configuration.