AN 737: SEU Detection and Recovery in Arria® 10 Devices

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ID 683064
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quartus® Prime Software SEU FIT Reports 3. Arria® 10 Error Detection and Correction Feature Architecture 4. Guidelines for Error Detection CRC and Error Correction Feature 5. Guidelines for Embedded Memory ECC Feature 6. Arria® 10 EDCRC Reference Design 7. Implementing ECC Feature in Arria® 10 ROM Design 8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
2. Quartus® Prime Software SEU FIT Reports x
2.1. Enabling the Projected SEU FIT by Component Usage Report 2.2. SEU FIT Parameters Report 2.3. Projected SEU FIT by Component Usage Report
2.3. Projected SEU FIT by Component Usage Report x
2.3.1. Component FIT Rates 2.3.2. Raw FIT 2.3.3. Utilized FIT 2.3.4. Mitigated FIT 2.3.5. Architectural Vulnerability Factor
2.3.3. Utilized FIT x
2.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 2.3.3.2. Considerations for Small Designs
3. Arria® 10 Error Detection and Correction Feature Architecture x
3.1. Error Detection and Correction for CRAM 3.2. Memory Blocks Error Correction Code Support
3.1. Error Detection and Correction for CRAM x
3.1.1. Error Detection Cyclic Redundancy Check 3.1.2. Recovering from CRC Errors
3.1.1. Error Detection Cyclic Redundancy Check x
3.1.1.1. Column-Based and Frame-Based Check-Bits 3.1.1.2. Error Message Register
4. Guidelines for Error Detection CRC and Error Correction Feature x
4.1. Error Detection 4.2. Enabling Error Correction (Internal Scrubbing) 4.3. Interpreting CRC_ERROR
4.1. Error Detection x
4.1.1. Enabling Error Detection 4.1.2. Reading EMR
4.1.1. Enabling Error Detection x
4.1.1.1. Enabling the Error Detection CRC_ERROR Pin
4.1.2. Reading EMR x
4.1.2.1. Reading EMR using EMR Unloader IP Core 4.1.2.2. Reading EMR using HPS 4.1.2.3. Reading EMR using JTAG Interface
4.3. Interpreting CRC_ERROR x
4.3.1. CRC_ERROR Pin Behavior 4.3.2. Correctable and Uncorrectable Error
6. Arria® 10 EDCRC Reference Design x
6.1. System Requirements 6.2. Creating Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys 6.3. Design Testing with Fault Injection Debugger
6.2. Creating Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys x
6.2.1. Starting Quartus® Prime Software and Opening the Reference Design Project 6.2.2. Creating New Qsys System 6.2.3. Generating Qsys System 6.2.4. Integrating Qsys System into Quartus Prime Project
6.2.2. Creating New Qsys System x
6.2.2.1. Specifying Target FPGA and Clock Settings 6.2.2.2. Adding Altera IOPLL IP Core 6.2.2.3. Adding EMR Unloader IP Core 6.2.2.4. Adding Advance SEU Detection IP Core 6.2.2.5. Adding Fault Injection IP Core 6.2.2.6. Adding Avalon-ST Splitter 6.2.2.7. Adding Serial Flash Controller
6.2.4. Integrating Qsys System into Quartus Prime Project x
6.2.4.1. Generating In-System Source and Probe IP Core 6.2.4.2. Quartus Prime Project Settings 6.2.4.3. Assigning ASD Regions 6.2.4.4. Assigning FPGA Pin Location 6.2.4.5. Compiling the Project
6.3. Design Testing with Fault Injection Debugger x
6.3.1. Converting .sof File and .smh File to .jic File 6.3.2. Programing .jic File into EPCQ-L 6.3.3. Launching Signal Tap Logic Analyzer 6.3.4. Configuring Arria® 10 and Reading .smh File with Fault Injection Debugger 6.3.5. Injecting Error with Fault Injection Debugger
7. Implementing ECC Feature in Arria® 10 ROM Design x
7.1. Examples of Error Detection and Correction
1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices

6.3.1. Converting .sof File and .smh File to .jic File

To program .sof file and .smh file into EPCQ-L, you must convert them to a .jic file. The converted .jic file is consist of:

  • The bit stream for Arria® 10 FPGA configuration in Active Serial mode upon power up
  • The .smh file content at certain offset that you can define in Convert Programming File tool

To convert, perform the following steps:

  1. Go to your output_files folder, duplicate the top.smh file and rename it to top.hex.
    Note: The .smh file is in Intel HEX standard format, i.e. bytes addressing little endian. You may need to convert the .smh file to match the endianness of your system
  2. Launch Convert Programming File tool from File menu.
  3. At Output programming file section, select JTAG Indirect Configuration File (.jic) from the Programming file type list.
  4. Select EPCQL1024 from Configuration device list.
  5. Select Active Serial x4 from Mode list.
  6. Give the File name as output_files/top.jic.
    Optional to check Create Memory Map File (Generate top.map) and Create config data RPD (Generate top_auto.rpd).
  7. At Input files to convert section, select Flash Loader at the column of File/Data area.
  8. Click Add Device button and select Arria 10, 10AX115S2 and click OK.
  9. Select SOF Data at File/Data area column, click Add File button and select the top.sof inside the output_files folder.
  10. Select top.sof under SOF Data, click the Properties button, enable Compression and click OK to close the SOF File Properties dialog.
  11. Click Add Hex Data at Input files to convertsection.
  12. Select Relative addressing and set the start address to 0x2000000. Leave Big endian as the default selection for Endianness. Select top.hex from your output_files folder, and click OK.
    The figure below shows the final setting for the .jic file generation. Verify and click Generate button.
  13. Click Close button to close the Convert Programming File after .jic is generated successfully.
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