Visible to Intel only — GUID: pqh1631598811077
Ixiasoft
1. Overview
2. Quartus® Prime Software SEU FIT Reports
3. Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Arria® 10 Devices
Visible to Intel only — GUID: pqh1631598811077
Ixiasoft
2.3. Projected SEU FIT by Component Usage Report
The Projected SEU FIT by Component Usage report shows the different components (or cell types) that comprise the total FIT rate, and SEU FIT calculation results.
An Intel FPGA's sensitivity to soft errors varies by process technology, component type, and your design choices when implementing the component (such as tradeoffs between area/delay and SEU rates). The report shows all bits (the raw FIT), utilized bits (only resources the design actually uses), and the ECC-mitigated bits.
Figure 2. Projected SEU FIT by Component Usage Report