Visible to Intel only — GUID: sss1429693533149
Ixiasoft
Visible to Intel only — GUID: sss1429693533149
Ixiasoft
3.1.1.1. Column-Based and Frame-Based Check-Bits
EDCRC Check-Bits Updates
Frame-based check-bits are calculated on-chip during configuration. Column-based check-bits are updated after configuration.
When you enable the EDCRC feature, after the device enters user mode, the EDCRC function starts reading CRAM frames. The data collected from the read-back frame is validated against the frame-based check-bits.
After the initial frame-based verification is completed, the column-based check-bits is calculated based on the respective column CRAM. The EDCRC hard block recalculates the column-based check-bits in one of the following scenarios:
- FPGA re-configuration
- After successful partial reconfiguration (PR) session
- After configuration via protocol (CvP) session