Visible to Intel only — GUID: vmo1687883612990
Ixiasoft
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
8.2. Power Delivery Overview
8.3. Board Power Delivery Network Recommendations
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
8.5. PCB PDN Design Guideline for Unused GTS Transceiver
8.6. PCB Voltage Regulator Recommendation for PCB Power Rails
8.7. Board Power Delivery Network Simulations
8.8. Agilex™ 5 Device Family PDN Design Summary
Visible to Intel only — GUID: vmo1687883612990
Ixiasoft
8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
Figure 73. Recommended Agilex™ 5 E-Series and D-Series Devices Power Tree with Non-SmartVID for Engineering Sample (ES) Devices This power tree demonstrates the recommended FPGA PCB power rails grouping. You can use any recommended voltage regulators listed in the FPGA Core Fabric VCC Voltage Regulator Selection section.
- This block diagram is applicable for the Agilex™ 5 E-Series and D-Series ES devices with Non-SmartVID and GTS Transceiver in the package.
- All power rails with naming _GTS refer to the GTS transceiver power rails.