PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)

The MIPI channel design must meet the MIPI standard board electrical specification. In the MIPI design, board traces, vias, connectors and cables are part of the board specification, while silicon and package are excluded. The following figure shows the supported standard reference channel up to 3.5 Gbps with respect to the maximum board trace length.

Figure 69. Standard Reference Channel Example to Support up to 3.5 Gbps

To meet the MIPI standard electrical specification on a MIPI interface, board designers must follow these guidelines:

  • The signal trace impedance on board is recommended to be 100-ohm differential. If the differential channel is also used for LP single-ended signal, it is recommended to apply loosely coupled differential transmission line.
  • Altera recommends using backdrill to minimize the impact of stub on signal transition vias, if performance is not good after the channel simulation.
  • Skew matching must be controlled within ±40 mil between data to clock signals.
  • In addition, keep 3 × h for intra-pair spacing while 5 × h for inter-pair spacing, where 'h' is the distance from the signal layer to the closest reference layer..
  • Avoid routing noisy signals such as CLK signals or VR modules near to MIPI signals; also, avoid having MIPI signals reference a noisy power plane.

The supported MIPI data rate varies based on two different MIPI board trace settings (length):

  • Long reference channel on PCB is supported up to 2.5 Gbps.
  • Standard reference channel is supported up to 3.5 Gbps.

The maximum routing length on PCB should be estimated to meet the loss requirement.

Table 17.  Supported MIPI Data Rate and Board Electrical Specifications
Data Rate (Gbps) 2.5 3.5
Supported Reference Channel Long Standard
Insertion Loss Frequency at 1.25 GHz -6.3 dB ±0.5 dB -3.75 dB ±0.5 dB
Insertion Loss Frequency at 5 GHz -20 dB ±0.8 dB -11.8 dB ±0.7 dB
Table 18.  MIPI 3.5 Gbps Board Electrical SpecificationsDetailed requirements for MIPI 3.5 Gbps.
Board Inter-Lane Common Mode Cross Coupling (dB)

< -40 dB

< 10.75*F-40.2188

0 < F ≤ 20 MHz

20 MHz < F ≤ 2.625 GHz
Differential Return Loss (dB) < -12 dB 0 < F ≤ 2.625 GHz
Board Inter-Lane Differential Cross Coupling (dB)

< -40 dB

< 5.37*F-40.1074

0 < F ≤ 20 MHz

20 MHz < F ≤ 2.625 GHz
Board Intra-Lane Cross Coupling < -20 dB 0 < F ≤ 200 MHz
Differential to common-mode conversion and vise versa < -26 dB 0 < F ≤ 2.625 GHz
Note: Altera® recommends following the comprehensive TLIS specification in MIPI DPHY V2.1.
Level Two Title