PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface BGA Breakout Optimization 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface

  • Intra pair skew: ±1mil

BGA Breakout Optimization

Through hole vias with backdrill are used. As outlined in the General Design Considerations section, note the change of impedance control tolerance, total insertion loss and so forth for microstrip routing. Altera recommends 3D field solver simulation for BGA breakout optimization. Try to make return loss lower than -15 dB at Nyquist frequency (lower than -20 dB is better) and control the impedance changing of cut-out area as small as possible (better within ±5 ohm). The following figures show detailed structures used on SOM for top layer and L3 fan-out. The following figures show the simulation results of return loss and TDR where the drill hole size of 8 mils and pad size of 16 mils is used. Simulation results for 18 mils pad size have been also presented. Both pad sizes can get good performance.

Figure 24. 85 Ω Top Layer Breakout Structure
Figure 25. 85 Ω L3 Breakout Structure
Figure 26. Simulation Results of Return Loss Using 16 mils Pad SizeFor top layer breakout (left) and L3 breakout (right).
Figure 27. Simulation Results of TDR Using 16 mils Pad SizeFor top layer breakout (left) and L3 breakout (right).

The impedance is lower due to the large capacitance caused by larger pad size of 18 mils. While the return loss is 3 to 4 dB higher, it meets the -15 dB requirement. A larger anti-pad size such as 30 mils can improve return loss performance as shown in the Simulation Results of L3 Breakout Using 18 mils Pad Size figure.

Figure 28. Simulation Results of L3 Breakout Using 18 mils Pad SizeUsing the same cut-out size (left) and larger anti-pad with 30 mils diameter (right).
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