PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

5.1. General DDR Signal Routing Guideline on PCB

General DDR Signal Routing Guideline on PCB

Altera recommends to route all data signals within a specific group on the same layer. Data Group signals (DQ, DM and DQS signals) are suggested to route on shallow layers (stripline or microstrip line) and use the shortest Z-height via transitions to avoid vertical crosstalk for better performance. Backdrilling can minimize the stub effect and achieve better performance, but this is not mandatory. You can run a simulation to determine whether to use backdrilling for deep layer routing. Long via stubs affects the channel ISI, however the impact of ISI is less than the impact of crosstalk for the max data rate performance.

Figure 50. Case A Routing is Suggested for Data Group Signals Over Case B

To minimize horizontal crosstalk between signals on the same layer, it is recommended to maintain adequate signal trace-to-trace (edge to edge) space, with a minimum spacing of 3xH separation distance for inner layer, where H is the dielectric thickness to the closest reference plane as illustrated in the following figure. Refer to following routing guide sections for detailed spacing requirements for each signal group.

Figure 51. Minimum Trace-to-Trace Separation Distance

FPGA DDR FPGA Break Out Routing

Agilex™ 5 devices come with various pitch sizes for different FPGA pins. For VPBGA package devices breakout, it is recommended to use a dog bone configuration, stripline routing for inner GPIO pins fan-out and microstrip routing for GPIO pins at edge of the device, as suggested in General VPBGA PCB Layout Guideline section. For MBGA devices breakout, refer to MBGA PCB routing guidelines. Both stripline and microstrip routing guidelines are presented in this chapter for all supported EMIF interfaces and topologies.

DQS and CLK signals in the DDR interface are differential signals. It is recommended to route DQS/CLK as differential signals and use a symmetrical fan-out at the FPGA pin field.

The following figure shows the symmetrical routing of differential signals (DQS/CLK) at FPGA pin field and the length/skew matching between P/N lanes.

Figure 52. Symmetrical Routing of Differential Signals (DQS/CLK) at FPGA Pin Field

DRAM Break Out in Layout Routing

For discrete DRAM components on PCB, you can either use the dog-bone or via in pad at DRAM for the signal transition from inner layer to DRAM. If dog-bone via transition is used, it is recommended to separate them with larger pitch to avoid crosstalk between signal vias.

Symmetrical routing of differential signals (DQS/CLK) in the DRAM pin area is limited due to very small pitch. Altera recommends routing the differential signals as single-ended signals within the DRAM pin field, ensuring to keep the same impedance while changing from differential to single-ended configuration. Designers must also keep the same routing length for single-ended lane P and N single-ended lane within the DRAM pin field. Applying the skew matching between P/N lanes before reaching the DRAM pin field improves performance.

The following figure shows the single-ended routing for differential signals (DQS/CLK) at DRAM pin field when the pitch is very small along with skew matching.

Figure 53. Symmetrical Routing of Differential Signals (DQS/CLK) at FPGA Pin Field

Ground Plane and Return Path

A continuous and solid ground reference plane is crucial for data lines. Low impedance ground return path from the FPGA to DRAM devices should be provisioned. In addition, it is desirable to keep the distance between the ground stitching vias and signal transition within 80mils for better signal via return path and better signal integrity performance.

General Notes for EMIF Routing Guidelines Table

The following general notes apply to the EMIF routing guidelines tables in subsequent topics:
  • All spacing requirements are the minimum requirement to be met on PCB in EMIF routing guidelines table.
  • In the routing guideline table, h represents the trace-to-nearest-reference-plane height or distance. Board designer should use the formula in the routing guide table to calculate the correct spacing requirements.
  • There is no differential impedance target for CLK and DQS. As a board designer, you should follow the EMIF routing table and keep traces closely coupled.
  • The trace length and spacing in guideline table are based on FR-4 level PCB material and the PCB layout routing with the worst-case crosstalk. You can perform simulation if not following the requirements in the routing guide table.
  • SL stands for stripline routing recommendation and US stands for upper surface (microstrip) routing recommendation in guideline tables.
  • You need to design trace widths of BO, BO1, BO2 and BI based on the actual PCB stack-up and PCB design. It would be better if trace widths of BO, BO1, BO2 and BI can be designed closer to target impedance of the M segment.
  • Include the FPGA package per-pin skew and PCB delay for skew matching.
  • Does not require length matching on the Alert signal and Reset signal.
  • Recommended to perform skew matching in time (picosecond).
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