PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary

The following table shows the PCB recommended FPGA decoupling capacitor requirement for the Agilex™ 5 device packages.

Fabric or core decoupling capacitors are highly dependent on the size of the core or fabric (LE and number of GPIO pins) in the package.

Table 27.   Agilex™ 5 device FPGA Decoupling Capacitors Summary
Device Agilex™ 5 Power and Thermal Calculator (PTC) Rail Name Bottom Side Capacitors FPGA Periphery Capacitors Notes

FPGA A5E007B

B15A/B23B/B18A/B23A Fabric

 Merged VCC and VCCP 2x 4.7uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E013B

B23A/B32A/M16A/B23B/B18A Fabric

 Merged VCC and VCCP 4x 10uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E028B

B23A/B32A/M16A/B23B Fabric

 Merged VCC and VCCP 4x 10uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E065B

B23A/B32A Fabric

 Merged VCC and VCCP 4x 10uF 0402 2x 47uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5E028A

B23A/B32A/M16A/B23B Fabric

 Merged VCC and VCCP 6x 10uF 0402 — VR vendors capacitors recommendation must be compiled.

FPGA A5E065A

B23A/B32A Fabric

 Merged VCC and VCCP 6x 10uF 0402 6x 47uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5D031

B23D/B32B Fabric

 Merged VCC and VCCP 6x 10uF 0402 4x 47uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.

FPGA A5D064

B32B Fabric

 Merged VCC and VCCP 8x 10uF 0402 8x 47uF 0805 VR vendors capacitors recommendation must be compiled. Use 47uF 0805 periphery capacitors on top-layer near FPGA.
FPGA/HPS VCCL_HPS 2x 10uF 0402 or 3x 4.7uF 0201 1x 22uF 0603 —
FPGA/HPS VCCL_HPS_CORE 1x 1uF 0201 — Per HPS_CORE, CORE0_CORE1, CORE2, and CORE3.
FPGA/HPS

VCCPLL1_HPS

VCCPLL2_HPS

 1x 1uF 0201 LC filter capacitors —
FPGA/HPS VCCIO_HPS 1x 1uF 0201 — —
FPGA/HPS

VCCPLLDIG1_HPS

VCCPLLDIG2_HPS

 1x 1uF 0201 LC filter capacitors —
FPGA VCCPT 2x 4.7uF 0201 1x 10uF 0402 —
FPGA VCCRCORE 1x 1uF 0201 1x 10uF 0402 —
FPGA/PIO VCCIO_PIO 2x 4.7uF 0201 1x 10uF 0402 Per IO bank
FPGA/SDM VCCH_SDM 1x 1uF 0201 — —
FPGA/SDM VCCL_SDM 2x 1uF 0201 — —
FPGA/SDM VCC_IO_SDM 1x 1uF 0201 — —
FPGA/SDM VCCL_ADC_SDM 1x 1uF 0201 — —
FPGA/SDM VCCPLLDIG_SDM 1x 1uF 0201 LC filter capacitors —
FPGA/SDM VCCIO_PIO_SDM 1x 1uF 0201 — —
FPGA/SDM VCCADC 1x 1uF 0201 LC filter capacitors —
FPGA/SDM VCCPLL_SDM 1x 1uF 0201 LC filter capacitors —
FPGA/SDM VCCIO_SDM 1x 1uF 0201 1x 10uF 0402 —
FPGA/SDM VCCFUSEWR_SDM 1x 1uF 0201 1x 4.7uF 0402 —
FPGA/HVIO VCCPT_HVIO 2x 1uF 0201 — Per IO bank
FPGA/HVIO VCCIO_HVIO 1x 1uF 0201 — Per IO bank
Level Two Title