PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

3.3.6. PCB Traces

  • Use stripline routing for better far end crosstalk performance and a tight impedance tolerance. Keep trace length shorter than the maximum allowed length limited by the full-channel insertion loss (IL) and eye diagram simulation results.
  • Consider microstrip routing for a PCB design with fewer layers, however note that the impedance control tolerance and total insertion loss may change. Altera recommends performing a simulation to verify these for microstrip.
  • Follow the general stripline pair-to-pair spacing rule of 5H for transmitter-to-transmitter and receiver-to-receiver, 9H for transmitter-to-receiver, transmitter-to-others, and receiver-to-others, where 'H' is the distance from the signal layer to the closest reference layer.
  • Use a solid ground reference for high-speed differential pairs.
  • Keep at least 5H of spacing between the edge of a trace and the void and between the edge of a trace and the edge of the reference plane in the open field area.
  • Maintain symmetrical routing between two signals that comprise a differential pair from end to end, including the trace length, the transition via location, and the placement of AC coupling capacitors. Failure to maintain routing symmetry introduces differential-to-common-mode or common-to-differential-mode conversion AC noise.
Figure 18. Symmetrical and Non-symmetrical Routing Examples
  • Breakout routing usually has a smaller trace width and smaller pair-to-pair spacing. Keep the breakout routing as short as possible to minimize the reflection and the insertion loss, and reduce the crosstalk.
  • To mitigate near end crosstalk, route the high-speed transmitter and receiver signals on different layers, or separate the TX and RX signals with large spacing of at least 9H in the stripline layer.
  • In the BGA pin field via array, avoid high-speed traces routing between two vias that comprise a differential pair via. Make the coupling area between the high-speed trace and via as small as possible.
  • To increase the common mode noise immunity, start differential pair P/N deskew at the transmitter, end deskew at the receiver, and compensate for the skew after the skew happens and close to the point where the variation occurs.
Figure 19. Intrapair Deskew Close to the Skew Happening Location
  • Minimize serpentine layouts, making them transparent to the signal, because serpentine layouts introduce discontinuity to the differential channel. You can minimize them by making electrical length shorter than the signal rise time. In general, keep the serpentine routing length <100 mils with arcs and bends of 45 degrees. A loosely coupled differential pair is less affected by serpentine lines.
Figure 20. Deskew Trombone Routing Rule
  • Use arc routing for high-speed differential traces.
  • Use teardrop traces for high-speed differential traces in the pad and via area.
  • Mitigate the fiber weave effect with techniques like zig-zag routing and image rotation.

The following figure shows zig-zag routing. If the weave is aligned to the PCB edges, follow a zig-zag routing of differential traces. Generally, maintain a minimum angle of 10 degrees between the trace and fiber weave; and the angles are relative to the PCB edge. For more details about the fiber weave effect, refer to AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing.

Figure 21. Zig-Zag Routing

Another solution is the image rotation that maintains an angle between the trace and the fiber weave pattern. Rotate until the traces are at a 10° angle relative to the fiber weave. Rotate by cutting the PCB at an angle, as shown in the following figure, or by rotating the layout relative to the edge of the PCB. It is recommended to evaluate the PCB cost change with the PCB vendor if using this method.

Figure 22. Cutting the PCB BoardThis figure describes Cutting the PCB Board to Rotate the Image Relative to the Fiber Weave Pattern.

For more information, refer to AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing.

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