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1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
8.2. Power Delivery Overview
8.3. Board Power Delivery Network Recommendations
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
8.5. PCB PDN Design Guideline for Unused GTS Transceiver
8.6. PCB Voltage Regulator Recommendation for PCB Power Rails
8.7. Board Power Delivery Network Simulations
8.8. Agilex™ 5 Device Family PDN Design Summary
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3.1. Overview of VPBGA
For VPBGA packaging board design, you must first understand the different ball pitches for different IO functions at different location in the package, then follow the guidance to plan the signal routing accordingly.
The following Agilex™ 5 A5E065B example shows the pin distribution for different functions.
Figure 6. Distribution of Pins for Different Functions in Agilex™ 5 A5E065B
Generally, power pins are concentrated in the middle area of BGA, GPIO pins are located at the north and south sides, and transceiver pins are spread at the east and west sides. Most Agilex™ 5 devices adopt VPBGA package and have different pitches in different BGA functional areas. In the transceiver and power areas, the pitch is 0.75 mm on the x-axis and 0.77 mm on the y-axis. In the GPIO area, including EMIF, the pitch is 0.65 mm, while every two columns have a larger spacing of approximately 1.45 mm for easier fan-out. The range of ball pitches of all Agilex™ 5 VPBGA devices is from 0.65 mm to 1.45 mm. For more details, refer to the specific device’s footprint.
Figure 7. Pitches in the Transceiver Area, GPIO Area Including DDR and Power Area
Altera recommends the dog-bone fan-out structure for Agilex™ 5 VPBGA devices.
Figure 8. Dog-bone Fan-out Structure
Take note that 0.65 mm ball pitch only exist on the outermost 2 rows for GPIO as shown in the yellow boxes in Example of 0.65 mm Pitch for B32A Package figure. Altera recommends to use microstrip for routing the GPIOs of the outermost 2 rows on the top layer to avoid PTH vias and simplify the inner layer routing.
This section shows the different ball pitch for different IO functions at different location in the package. It is important to understand the overall package design, then follow the guidance to plan the signal routing accordingly.
Figure 9. Example of 0.65 mm Pitch for B32A PackageYellow boxes indicate the locations of balls with 0.65mm ball pitch.
The 0.65 mm ball pitch is optimized to have one signal trace to route through on the top layer to facilitate easy routing as shown in Example of Fan-out for the Outermost Two Rows in GPIO area on Top Layer figure.
Figure 10. Example of Fan-out for the Outermost Two Rows in GPIO area on Top Layer
Typically, those pins are used as EMIF DQ group.
In the Example of Inner Layer Fan-out figure, the GPIO pins are located at the inner area of the BGA with every two columns have a spacing of approximately 1.45 mm, to fan-out up to 5 or 6 signal-ended signals depending on the specific stack-up design.
Figure 11. Example of Inner Layer Fan-out
Fan-out more signals on each layer to help to reduce the total layer count. You can consider implementing vias with 8 mils or 10 mils drill hole size. Refer to EMIF PCB Routing Guidelines section for detailed recommendations on spacing, length matching, max routing length, and so forth of EMIF signals with microstrip or stripline routing.
For transceiver BGA area, you can consider routing microstrip lines for fan-out on the top layer for high-density designs that need fewer PCB layers as shown in the Top Layer Fan-out Example with Differential Pairs figure. However, this changes the impedance control tolerance, total insertion loss and so forth. Hence, Altera recommends conducting simulations to verify.
Figure 12. Top Layer Fan-out Example with Differential Pairs
When the outer 2 rows of transceivers are routed with microstrip at top layer, you can use the differential pair routing in inner layer fan-out as shown in Inner Layer Fan-out Example with Differential Pairs.
Figure 13. Inner Layer Fan-out Example with Differential Pairs
Alternatively, you can also use single-ended traces for inner layer transceiver fan-out to meet the drill to metal requirement (D2M, usually 7 to 8 mils) as demonstrated in Inner Layer Fan-out Example with Single-ended Traces figure.
Figure 14. Inner Layer Fan-out Example with Single-ended Traces
For high-speed signal vias, use backdrilling technology to minimize the stub effect. You can find detailed simulation results of the reference design in GTS Transceiver PCIe Gen4 16 GT/s NRZ Interface Design Guidelines and GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines sections.
The power pins for Agilex™ 5 VPBGA devices are mainly located in the center BGA area, with some GPIO at the edge of the center BGA areas to ease the signal trace routing as shown in the Power and Ground Pins at the Center Area of VPBGA figure. You can find the current values and other relevant specs for each power rail in the Power Distribution Network Design Guidelines section. Altera recommends following the requirements in the PDN design guidelines. DC IR drop and PDN transient simulations during the post layout simulation stage are helpful for the design. For a lower inductance connection, it is advisable for power vias to have a solid and unbroken connection to the power planes.
Figure 15. Power and Ground Pins at the Center Area of VPBGA