PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

8.2.3.3. Power Nets and Transient Specifications

Rail transient values provided in the following table are used to design and simulate the board level transient power. Choose the recommended load slew rates and step load at FPGA package ball below for PCB-level PDN system simulations and design. The table shows the maximum tolerable step load at FPGA package pin. The recommended step load is connected to FPGA package ball along with the PCB post-layout model (with decoupling capacitors and voltage regulator model excluding package and silicon/die model) in an EDA tool for time domain simulation to meet rail tolerance of respective power net in the Power Rails Tolerance section at the FPGA package ball.

The table shows for the recommended step load at the package ball and step load’s slew rate.

Note: The step load suggested in the table is for a normal application and worst case operation in FPGA and tiles. The step load can also be scaled down if the dynamic current of the target power rail in PTC is smaller than the step load shown in the table.
Table 26.   Agilex™ 5 Device Family Transient and Step Load Specifications at Package Pin
Package Power Rails At Package Balls (Step Load) DI/dt at Package Balls (for Board Design)-Slew Rate Notes
DI (A)-Step Load DI/dt (A/µs)-Slew Rate

VCC&VCCP

A5E007B

B15A/B23B/B18A

 0.8 26 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5E013B

B23A/B32A/M16A/B23B/B18A

 1.5 50 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5E028B

B23A/B32A/M16A/B23B

 2.5 100 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5E065B

B23A/B32A

 3.5 70 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5E065A

B23A/B32A

 3.7 74 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5D031

B23D/B32B

 2 100 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.

VCC&VCCP

A5D064

B32B

 4.9 196 The step load is the worst case step load in the design based on 80% utilization of LAB and clock network.
VCCPT 0.05 7.14 —
VCCRCORE 0.2 5 —
VCCIO_PIO 0.645 10.8 Current specification is per I/O bank. Each I/O bank consists of 96 x I/Os. More I/O banks can join the same voltage regulator, but current specification stays per I/O bank.
VCCL_HPS 0.016 0.15 —
VCCL_HPS_CORE0_CORE1 0.01 0.1 —
VCCL_HPS_CORE2 0.02 0.2 —
VCCL_HPS_CORE3 0.014 0.14 —
VCC_HSSI 0.053 1.66 For X4 GTS transceiver banks
VCCERT_GTS 0.02 2 For single GTS transceiver channel
0.1 0.3 For X4 GTS transceiver channels
VCCEHT_GTS 0.01 0.37 For single GTS transceiver channel
0.07 0.23 For X4 GTS transceiver channels

You must also notice the following:

  1. Step current at package pin is only provided for critical power rails due to either having high current/power profile at die or being highly sensitive. Agilex™ recommends you to do transient/time domain PDN simulation by using this step load for these critical power rails in the Agilex™ 5 Device Family Transient and Step Load Specifications at Package Pin table to ensure you can meet the voltage specification at package pin. If the voltage specification is not met at package pin, decoupling capacitors must be adjusted.
  2. Altera does not provide step current for other power rails not mentioned in the Agilex™ 5 Device Family Transient and Step Load Specifications at Package Pin table. Those power rails are called non-critical power rails due to having less sensitivity or low current profile/power consumption on silicon. Altera does not recommend time domain PDN analysis for non-critical power rails. Non-critical power rails PDN design suggested in this application note is guaranteed.
  3. Altera recommends that you perform DC IR drop analysis for all power rails.
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