PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

8.2.3.2. Power Rails Tolerance

This section describes the power rails tolerance and budget (AC tolerance + VR accuracy) on board at package level for the Agilex™ 5 device family. The rail tolerance must be met at the FPGA package ball. You must consider the following instructions to measure the rail tolerance:

  • VCCL (core power net) measurement is taken at the FPGA remote differential sense lines (there are assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20 MHz.
  • Other power rails (except for VCCL (core power)), the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
  • For all other power rails with the objective to compensate the IR drop on those specific power rails, place their respective voltage regulator sense point within the FPGA pin field, connecting to one of the rail's BGA pins which represents the worst IR drop on the path.
Table 24.   Agilex™ 5 SmartVID Device PCB Power Rail Tolerance
Power Tree Rail Name

Vnom (Required)

(V)

Recommended VR Accuracy

(% of Vnom)

Recommended VR Ripple

(% of Vnom)

Recommended AC Transient

(% of Vnom)

Maximum AC Tolerance + VR Accuracy1

(% of Vnom)
VCCL SmartVID (0.8) ±0.5% ±2.5% ±3%
P0V8_GR1 0.8 ±0.5% ±2.5% ±3%
P1V0_GR1 1.0 ±0.5% ±2.0% ±2.5%

P1V8_GR2a2 :

  • VCCEHT_GTS
 1.8 ±0.5% ±2.0% ±2.5%

P1V8_GR2a2:

  • VCCPT_HVIO
 1.8 ±0.5% ±1%3 ±1.5% ±3%

P1V8_GR2a2:

  • VCCPT
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
  • VCCPLL1_HPS
  • VCCPLL2_HPS
  • VCCADC
  • VCCPLL_SDM
 1.8 ±0.5% ±1%3 ±3.5% ±5%

P1V2_GR2b4 :

  • VCCIO_PIO_T/B
  • VCCIO_PIO_SDM
 1.2 ±0.5% ±1%3 ±1.5% ±3%

P1V2_GR2b4:

  • VCCRCORE
 1.2 ±0.5% ±1%3 ±3.5% ±5%
VCCIO_HVIO 3.3/2.5/1.8 ±0.5% ±1%3 ±1.5% ±3%
Table 25.   Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance
Power Tree Rail Name

Vnom (Required)

(V)

Recommended VR Accuracy

(% of Vnom)

Recommended VR Ripple

(% of Vnom)

Recommended AC Transient

(% of Vnom)

Maximum AC Tolerance + VR Accuracy1

(% of Vnom)
VCCL

0.8 (-4S)

0.78 (-5S)

0.75 (-6S, -6X)

 ±0.5% ±2.5% ±3%
P1V0_GR1 1.0 ±0.5% ±2.0% ±2.5%

P1V8_GR2a2:

  • VCCEHT_GTS
 1.8 ±0.5% ±2.0% ±2.5%

P1V8_GR2a2:

  • VCCPT_HVIO
 1.8 ±0.5% ±1%3 ±1.5% ±3%

P1V8_GR2a2:

  • VCCPT
  • VCCIO_SDM
  • VCCIO_HPS
  • VCCFUSEWR_SDM
  • VCCPLL1_HPS
  • VCCPLL2_HPS
  • VCCADC
  • VCCPLL_SDM
 1.8 ±0.5% ±1%3 ±3.5% ±5%

P1V2_GR2b4:

  • VCCIO_PIO_T/B
  • VCCIO_PIO_SDM
 1.2 ±0.5% ±1%3 ±1.5% ±3%

P1V2_GR2b4:

  • VCCRCORE
 1.2 ±0.5% ±1%3 ±3.5% ±5%
VCCIO_HVIO 3.3/2.5/1.8 ±0.5% ±1%3 ±1.5% ±3%

The actual specification for each power rail at package level is listed in the Agilex™ 5 FPGAs and SoCs Device Data Sheet. To reduce the PCB cost, some power rails are merged by using only a single voltage regulator to feed the power rails. The AC + DC specification in this design guideline is based on this design. However, you have the option to not combine the power rails on the PCB in your design.

You can combine the analog power rails on the PCB (provided that the nominal voltages are the same) by using a single voltage regulator on the PCB to feed the power rails to achieve the minimum cost. If you implement this design, you must ensure the power rail specifications of the combined power rails on the PCB and voltage regulator must follow the most stringent specification of those package power rails.

The Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables show the power rail tolerance (AC tolerance + VR accuracy) based on the power tree in the Power Tree section.

If a different power tree is used, the rail tolerance of each power net must still fall into their recommended grouping category in the Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables.

Related Information
1 The specification stands for VR accuracy + (VR ripple + AC transient) rail tolerance and must be measured and met at package pin/ball.
2 Use the tight tolerance requirement in board design for P1V8_GR2a rail.
3 If you select a VR with lower than 1% VR ripple specification, the extra margin is added to recommended AC transient specification.
4 Use the tight tolerance requirement in board design for P1V2_GR2b rail.
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