PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 821801
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview of Agilex™ 5 Package 3. VPBGA PCB Layout Guideline 4. MBGA PCB Routing Guidelines 5. EMIF PCB Routing Guidelines (VPBGA and MBGA) 6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA) 8. Power Distribution Network Design Guidelines 9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs
2. Overview of Agilex™ 5 Package x
2.1. BGA Footprint and Land Pattern
3. VPBGA PCB Layout Guideline x
3.1. Overview of VPBGA 3.2. VPBGA HSSI Reference PCB Stack-up 3.3. General Design Considerations 3.4. Agilex™ 5 GTS Transceiver 3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines 3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines 3.7. Other Connectors
3.3. General Design Considerations x
3.3.1. Impedance Tolerances 3.3.2. Reference Planes 3.3.3. Layer Assignment 3.3.4. Via Drill Size 3.3.5. Fiber Weave 3.3.6. PCB Traces 3.3.7. PCB Vias 3.3.8. AC Coupling Capacitors 3.3.9. Others
3.4. Agilex™ 5 GTS Transceiver x
3.4.1. HSSI Pin-Field Breakout for VPBGA
3.5. GTS Transceiver PCIe* Gen4 16 GT/s NRZ Interface Design Guidelines x
3.5.1. GTS Transceiver Channel Recommendations 3.5.2. General Guidelines for GTS Transceiver PCIe* Gen4 Interface 3.5.3. PCIe* Add-in Card Edge Finger
3.6. GTS Transceiver Ethernet 25 Gbps NRZ Interface Design Guidelines x
3.6.1. GTS Transceiver Channel Recommendations 3.6.2. General Guidelines for GTS Transceiver Ethernet Interface 3.6.3. QSFP Connector Routing 3.6.4. SFP Connector Routing
3.7. Other Connectors x
3.7.1. ADM/F Connectors 3.7.2. DP and HDMI Connectors 3.7.3. FMC+ Connectors
5. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
5.1. General DDR Signal Routing Guideline on PCB 5.2. LPDDR5 Interface Design Guidelines 5.3. LPDDR4 Interface Design Guidelines 5.4. DDR4 Routing Guidelines 5.5. LPDDR5, LPDDR4 and DDR4 Simulation Strategy
5.4. DDR4 Routing Guidelines x
5.4.1. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies 5.4.2. Skew Matching Guidelines for DDR4 Memory Down Configurations 5.4.3. Power Delivery Recommendation for DDR4 Discrete Configurations
8. Power Distribution Network Design Guidelines x
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 8.2. Power Delivery Overview 8.3. Board Power Delivery Network Recommendations 8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 8.5. PCB PDN Design Guideline for Unused GTS Transceiver 8.6. PCB Voltage Regulator Recommendation for PCB Power Rails 8.7. Board Power Delivery Network Simulations 8.8. Agilex™ 5 Device Family PDN Design Summary
8.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
8.1.1. Device Guidelines Status for Agilex™ 5 Devices
8.2. Power Delivery Overview x
8.2.1. Power Architecture 8.2.2. Rail Merger Requirements 8.2.3. Power Rails Specification 8.2.4. Decoupling Capacitors Recommendation
8.2.1. Power Architecture x
8.2.1.1. Power Budget 8.2.1.2. Power Tree
8.2.1.2. Power Tree x
8.2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 8.2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
8.2.3. Power Rails Specification x
8.2.3.1. Power Nets 8.2.3.2. Power Rails Tolerance 8.2.3.3. Power Nets and Transient Specifications
8.2.3.1. Power Nets x
8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
8.2.4. Decoupling Capacitors Recommendation x
8.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 8.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
8.3. Board Power Delivery Network Recommendations x
8.3.1. Board Decoupling Capacitors Guide 8.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 8.3.3. Remote Sense Connections 8.3.4. Load Line Requirements 8.3.5. VCC Core Board Current Slew Rate
8.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
8.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
8.5. PCB PDN Design Guideline for Unused GTS Transceiver x
8.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Introduction
2. Overview of Agilex™ 5 Package
3. VPBGA PCB Layout Guideline
4. MBGA PCB Routing Guidelines
5. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
7. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
8. Power Distribution Network Design Guidelines
9. Document Revision History for the PCB High-Speed Signal Design Guidelines: Agilex™ 5 FPGAs and SoCs

8.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details

Table 21.   Agilex™ 5 E-Series and D-Series SmartVID FPGA Package Power Rail Nets and Subsystem Details
Device Power Thermal Calculator (PTC) Rail Name Board Connections System Connections
FPGA VCC VCCL, SmartVID, 0.8 V VCC supplies power to the Core.
FPGA/PIO VCCP VCCP supplies power to the Periphery.
FPGA/HPS VCCL_HPS VCCL_HPS suppliers’ power to the HPS DSU and periphery circuitry.
FPGA/HPS VCCPLLDIG1_HPS VCCPLLDIG1_HPS: Digital power supply of the main HPS PLLs.
VCCPLLDIG2_HPS VCCPLLDIG2_HPS: Digital power supply of the peripheral HPS PLLs.
FPGA/HPS VCCL_HPS_CORE0_CORE1 Supply power to HPS A55 Core0 and Core1.
FPGA/HPS VCCL_HPS_CORE2 Supply power to HPS A76 Core2.
FPGA/HPS VCCL_HPS_CORE3 Supply power to HPS A76 Core3.
FPGA/SDM VCC_IO_SDM SDM block I/O digital supply voltage sense.
FPGA/SDM VCCL_ADC_SDM HPS DSU and periphery voltage sense.
FPGA/SDM VCCL_SDM P0V8_GR1 SDM power supply.
FPGA/SDM VCCPLLDIG_SDM SDM block PLL power pins.
FPGA/SDM VCCH_SDM P1V0_GR1

Voltage rail sense.

It is 0.8 V and can be combined with VCCL_SDM for the devices without GTS transceiver.
FPGA VCCPT P1V8_GR2a Power supply for the IOPLL, programmable power technology, and I/O pre-drivers.
FPGA/HVIO VCCPT_HVIO Pre-driver analog power supply pin for HVIO.
FPGA/SDM VCCIO_SDM Configuration pins power supply.
FPGA/HPS VCCIO_HPS The HPS dedicated I/Os support 1.8 V voltage level.
FPGA/SDM VCCFUSEWR_SDM The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ Security architecture.
FPGA/HPS VCCPLL1_HPS VCCPLL1_HPS: Supply analog power to the main HPS PLLs.
VCCPLL2_HPS VCCPLL2_HPS: Supply analog power to the peripheral HPS PLLs.
FPGA/SDM VCCADC ADC power pin for the voltage sensors.
FPGA/SDM VCCPLL_SDM VCCPLL_SDM supplies analog power to the SDM block PLLs.
FPGA/PIO VCCIO_PIO_T/B P1V2_GR2b Power supply voltage pins for the I/O banks.
FPGA/SDM VCCIO_PIO_SDM VCCIO_PIO voltage rail sense line.
FPGA VCCRCORE Transceiver core power supply.
FPGA/HVIO VCCIO_HVIO P3V3/2V5/1V8_GR2b Buffer analog power supply pin for HVIO.
FPGA/SDM VCCBAT VCCBAT Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.
Table 22.   Agilex™ 5 E-Series and D-Series Non-SmartVID FPGA Package Power Rail Nets and Subsystem Details
System Power Thermal Calculator (PTC) Rail Name Board Connections System Connections
FPGA VCC VCCL 0.8 V/0.78 V/0.75 V VCC supplies power to the Core.
FPGA/PIO VCCP VCCP supplies power to the Periphery.
FPGA/HPS VCCL_HPS VCCL_HPS suppliers’ power to the HPS DSU and periphery circuitry.
FPGA/HPS VCCPLLDIG1_HPS VCCPLLDIG1_HPS: Digital power supply of the main HPS PLLs.
VCCPLLDIG2_HPS VCCPLLDIG2_HPS: Digital power supply of the peripheral HPS PLLs.
FPGA/HPS VCCL_HPS_CORE0_CORE1 Supply power to HPS A55 Core0 and Core1.
FPGA/HPS VCCL_HPS_CORE2 Supply power to HPS A76 Core2.
FPGA/HPS VCCL_HPS_CORE3 Supply power to HPS A76 Core3.
FPGA/SDM VCC_IO_SDM SDM block I/O digital supply voltage sense.
FPGA/SDM VCCL_ADC_SDM HPS DSU and periphery voltage sense.
FPGA/SDM VCCL_SDM SDM block I/O digital supply voltage sense.
FPGA/SDM VCCPLLDIG_SDM HPS DSU and periphery voltage sense.
FPGA/SDM VCCH_SDM P1V0_GR1

Voltage rail sense.

It can be 0.8 V/0.78 V/0.75 V according to the speed grade, and can be combined with VCCL_SDM for the devices without GTS transceiver.

FPGA VCCPT P1V8_GR2a Power supply for the IOPLL, programmable power technology, and I/O pre-drivers.
FPGA/HVIO VCCPT_HVIO Pre-driver analog power supply pin for HVIO.
FPGA/SDM VCCIO_SDM Configuration pins power supply.
FPGA/HPS VCCIO_HPS The HPS dedicated I/Os support 1.8 V voltage level.
FPGA/SDM VCCFUSEWR_SDM The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ Security architecture.
FPGA/HPS VCCPLL1_HPS VCCPLL1_HPS: Supply analog power to the main HPS PLLs.
VCCPLL2_HPS VCCPLL2_HPS: Supply analog power to the peripheral HPS PLLs.
FPGA/SDM VCCADC ADC power pin for the voltage sensors.
FPGA/SDM VCCPLL_SDM VCCPLL_SDM supplies analog power to the SDM block PLLs.
FPGA/PIO VCCIO_PIO_T/B P1V2_GR2b Power supply voltage pins for the I/O banks.
FPGA/SDM VCCIO_PIO_SDM VCCIO_PIO voltage rail sense line.
FPGA VCCRCORE Transceiver core power supply.
FPGA/HVIO VCCIO_HVIO P3V3/2V5/1V8_GR2b Buffer analog power supply pin for HVIO.
FPGA/SDM VCCBAT VCCBAT Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.
Table 23.   Agilex™ 5 GTS Transceiver Power Rail Nets and Subsystem Details
PTC Rail Name Board Connections SystemConnections
VCC_HSSI P0V8_GR1 SmartVID devices, GTS transceiver digital logic power supply.
VCC_HSSI VCCL 0.8 V/0.78 V/0.75 V Non-SmartVID devices, GTS transceiver digital logic power supply.
VCCERT_GTS P1V0_GR1 GTS transceiver analog 1.0 V logic power pins.
VCCEHT_GTS P1V8_GR2a GTS transceiver high-voltage analog power supply pins.
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