Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.5.10. PHY Interfaces

The following figure shows the USB 3.1 Gen1 controller PHY interfaces.

Figure 171. PHY Interfaces

The USB 3.1 controller supports ULPI interface to PHY for USB2.0 operations and PIPE3 interface to GTS transceiver for Super-Speed mode. The ULPI interface of the USB 3.1 controller is connected to dedicated I/O pins of the HPS through pin multiplexers. The pin multiplexers are controlled by the system manager registers.

In host mode, both USB 2.0 and USB 3.1 operations can be simultaneously active to concurrently support USB 2.0 and USB 3.1 devices. However, in device mode, because the controller connects as either a USB 2.0 device or a USB 3.1 device, only one of these operations is active at a given time.